Intel SL3VS - Celeron 633 MHz Processor Specification page 95

15. Page B-41, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction.
Entry PMULL currently states:
PMULL – Packed multiplication
It should state:
PMULLW – Packed multiplication, store low word
C13. RSM Instruction Set Summary
The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture Section 5.8 "INSTRUCTION
SET SUMMARY" currently states:
RSM Return from system management mode (SSM)
It should state:
RSM Return from system management mode (SMM)
C14. Correct MOVAPS and MOVAPD Operand Section
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Section 3.2
"INSTRUCTION REFERENCE" MOVAPS and MOVAPD operation section currently states:
Operation
DEST SRC;
It should state:
Operation
DEST SRC;
•
#GP if SRC or DEST unaligned memory operand *;
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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