Intel SL3VS - Celeron 633 MHz Processor Specification page 64

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C62. Processor May Assert DRDY# on a Write With No Data
When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that one chunk
Problem:
has a mask of all 0's, the processor will initiate two partial write transactions with one having all byte enables
deasserted. Under these conditions, the expected behavior of the processor would be to perform both write
transactions, but to deassert DRDY# during the transaction which has no byte enables asserted. As a result of
this erratum, DRDY# is asserted even though no data is being transferred.
The implications of this erratum depend on the bus agent's ability to handle this erroneous
Implication:
DRDY# assertion. If a bus agent cannot handle a DRDY# assertion in this situation, or attempts to use the
invalid data on the bus during this transaction, unpredictable system behavior could result.
A system which can accept a DRDY# assertion during a write with no data will not be affected
Workaround:
by this erratum. In addition, this erratum will not occur if the MASKMOVQ is aligned.
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C63. Machine Check Exception May Occur Due to Improper Line
Eviction in the IFU
The Celeron processor is designed to signal an unrecoverable Machine Check Exception (MCE)
Problem:
as a consistency checking mechanism. Under a complex set of circumstances involving multiple speculative
branches and memory accesses there exists a one cycle long window in which the processor may signal a
MCE in the Instruction Fetch Unit (IFU) because instructions previously decoded have been evicted from the
IFU. The one cycle long window is opened when an opportunistic fetch receives a partial hit on a previously
executed but not as yet completed store resident in the store buffer. The resulting partial hit erroneously
causes the eviction of a line from the IFU at a time when the processor is expecting the line to still be present.
If the MCE for this particular IFU event is disabled, execution will continue normally.
While this erratum may occur on a system with any number of Celeron processors, the
Implication:
probability of occurrence increases with the number of processors. If this erratum does occur, a machine
check exception will result. Note systems that implement an operating system that does not enable the
Machine Check Architecture will be completely unaffected by this erratum (e.g., Windows* 95 and Windows
98).
It is possible for BIOS code to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C65. Snoop Request May Cause DBSY# Hang
A small window of time exists in which a snoop request originating from a bus agent to a
Problem:
processor with one or more outstanding memory transactions may cause the processor to assert DBSY#
without issuing a corresponding bus transaction, causing the processor to hang (livelock). The exact
circumstances are complex, and include the relative timing of internal processor functions with the snoop
request from a bus agent.
This erratum may occur on a system with any number of processors. However, the probability
Implication:
of occurrence increases with the number of processors. If this erratum does occur, the system will hang with
DBSY# asserted. At this point, the system requires a hard reset.
It is possible for BIOS code to contain a workaround for this erratum.
Workaround:
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