Intel SL3VS - Celeron 633 MHz Processor Specification page 101

C22. Cache Description
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Table 3-10, the
"sectored, 64 byte line size" description is used for the following descriptors: 0x22, 0x23, 0x79, 0x7a,
0x7b, 0x7c. This description will change to "dual-sectored line, 64 byte sector size" for clarity.
C23. Instruction Formats and Encoding
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Page B-8, CMOVcc
memory to register should be encoded as "0000 1111 : 0100 tttn : mod reg r/m". Page B-8, CMP immediate
with memory should be encoded as "1000 00sw : mod 111 r/m : immediate data". Page B-12 POP "segment
register CS, DS, ES" should be encoded as "segment register DS, ES".
C24. Machine-Check Initialization
The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide
currently states :
14.5 MACHINE-CHECK INITIALIZATION
To use the processors machine-check architecture, software must initialize the processor to activate the
machine-check exception and the error-reporting mechanism.
Example gives pseudocode for performing this initialization. This pseudocode checks for the existence of the
machine-check architecture and exception on the processor, then enables the machine-check exception and
the error-reporting register banks. The pseudocode assumes that the machine-check exception (#MC) handler
has been installed on the system. This initialization procedure is compatible with the Pentium 4, Intel Xeon, P6
family, and Pentium processors.
Following power up or power cycling, the IA32_MC i _STATUS registers are not guaranteed to have valid data
until after the registers are initially cleared to all 0s by software, as shown in the initialization pseudocode in
Example .
EXECUTE the CPUID instruction;
READ bits 7 (MCE) and 14 (MCA) of the EDX register;
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Machine-Check Initialization Pseudocode
section 14.5
93