Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU Specification
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Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU Specification

Processor on 90 nm process
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R
®
Intel
Pentium
90 nm Process
Specification Update
September 2006
®
Notice: The Intel
Pentium
as errata which may cause the product to deviate from published specifications.
Current characterized errata are documented in this Specification Update.
®
4 Processor on
®
processor may contain design defects or errors known
Document Number:
302352-031

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Summary of Contents for Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU

  • Page 1 90 nm Process Specification Update September 2006 ® ® Notice: The Intel Pentium processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

  • Page 3: Table Of Contents

    Summary Tables of Changes ..................... 8 General Information ......................21 Identification Information....................23 Errata ..........................30 Specification Changes ...................... 73 Specification Clarifications ....................74 Documentation Changes ....................75 § ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...

  • Page 4: Revision History

    Revision History Revision Description Date Number • Initial Release -001 June 2004 • Added content for Intel ® ® -002 Pentium 4 processor on 90 nm process in 775-land package • Added 775-land package processor upside marking diagram in Figure 2 “Out-of-Cycle”...
  • Page 5 -029 May 2006 • Added erratum R122, updated processor identification table -030 June 2006 • Updated R93, added R123, and updated processor identification -031 September 2006 table § ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...

  • Page 6: Preface

    Architecture Software Developer's Manual Volume 2B: entium4/manuals/index_new.htm Instruction Set Reference Manual, N–Z, document 253667 IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668 IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669 ®...
  • Page 7 Care should be taken to read all notes associated with each S-Spec number ® ® Errata are design defects or errors. Errata may cause the Intel Pentium processor’s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 8: Summary Tables Of Changes

    The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Pentium 4 processors on 90 nm process. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
  • Page 9 Z = Mobile Intel Pentium 4 processor with 533 MHz system bus ® ® ® ® AA = Intel Pentium processor Extreme Edition and Intel Pentium D processor on 65nm process ® ® AB = Intel Pentium 4 processor on 65 nm process ®...
  • Page 10 Near Branch (Jump or Call) Fixed May Cause an Incorrect Address to be Reported to the #GP Exception Handler Bus Locks and SMC Detection May Cause the Processor to Hang Temporarily ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 11 The State of the Resume Flag (RF Fixed Flag) in a Task-State Segment (TSS) May be Incorrect Using STPCLK# and Executing Code From Very Slow Memory Could Lead to a System Hang ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 12 IRET Instruction Performing Task Fixed Switch May Not Serialize the Processor Execution Incorrect Access Controls to Fixed MSR_LASTBRANCH_0_FROM_LI P MSR Registers Recursive Page Walks May Cause Fixed a System Hang ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 13 EM64T)Φ Upper 32 Bits of FS/GS with Null Base May not get Cleared in Virtual-8086 Mode on Processors Fixed with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Processor May Fault when the Upper 8 Bytes of Segment Selector is Loaded From a Far Jump...
  • Page 14 The Base of an LDT (Local Descriptor Table) Register May be Non-zero on a Processor Fixed Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) L-bit of the CS and LMA bit of the IA32_EFER Register May Have an Erroneous Value For One...
  • Page 15 Fail to Execute to Completion or May Write to Incorrect Memory Fixed Locations on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) An REP LODSB or an REP LODSD or an REP LODSQ Instruction with RCX >= 2^32 May Cause a System...
  • Page 16 Memory 64 Technology (Intel® EM64T) Upper Reserved Bits are Incorrectly Checked While Loading PDPTR's Fixed on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported Incorrectly in the Branch Trace...
  • Page 17 May Cause an Unexpected Interrupt Access to an Unsupported Address Range in Uniprocessor (UP) or Dual-processor (DP) Systems Supporting Intel® Virtualization Technology May Not Trigger Appropriate Actions VM Exit Due to a MOV from CR8 R100 May Cause an Unexpected Memory...
  • Page 18 Only applies to Pentium 4 processor on 90 nm Process in the 478-pin package Prefix “L” denotes Pentium 4 processor on 90 nm Process in the 775-land LGA package ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 19 Extended Memory 64 Technology (Intel EM64T) for Single-Processor Server/Workstation Platform configurations only. Non-server/workstation desktop configurations do not support the Intel Extended Memory 64 Technology. This erratum does not apply to Pentium 4 processors for single-processor server/workstation platform configurations. For these steppings, this erratum may be worked around in BIOS.
  • Page 20 Summary Tables of Changes ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...

  • Page 21: General Information

    General Information General Information ® ® Figure 1. Intel Pentium 4 Processor on 90 nm Process in the 478-pin Package Copyright Info Brand INTEL Product Code PENTIUM® 4 SSPEC/Country X.XXGHZ / 1M / 800 of Assy SLXXX MALAY BBBBBBBB ATPO...
  • Page 22 General Information Δ ® ® Figure 4. Intel Pentium 4 Processor 670, 660, 650, 640, and 630 on 90 nm Process in the 775-Land LGA Package ® ® Figure 5. Intel Pentium 4 Processor Extreme Edition on 90 nm Process in the 775-Land LGA Package §...

  • Page 23: Identification Information

    CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan. ® ® Table 1. Intel Pentium 4 Processor on 90 nm Process Processor Identification Information...
  • Page 24 Identification Information ® ® Table 1. Intel Pentium 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 35.0 x 35.0 mm SL7E2 0F34h 2.80GHz/533MHz 2, 4, 7 FC-mPGA4 Rev 2.0...
  • Page 25 Identification Information ® ® Table 1. Intel Pentium 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 775-land FC-LGA4 SL7J7 0F34h 3.20GHz/800MHz 4, 8, 11 37.5 x 37.5 mm Rev 01...
  • Page 26 Identification Information ® ® Table 1. Intel Pentium 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 775-land FC-LGA4 SL7PT 0F41h 2.66GHz/533MHz 4, 8, 15, 19 37.5 x 37.5 mm Rev 01...
  • Page 27 Identification Information ® ® Table 1. Intel Pentium 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 775-land FC-LGA4 SL84X 0F41h 3.60GHz/800MHz 1, 4, 9, 11, 13, 14, 15 37.5 x 37.5 mm Rev 01...
  • Page 28 Identification Information ® ® Table 1. Intel Pentium 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 775-land FC-LGA4 SL8PN 0F49h 3.06GHz/533MHz 4, 8, 12, 13, 14, 15, 19 37.5 x 37.5 mm Rev 01...
  • Page 29 37.5 x 37.5 mm Rev 01 16, 17, 18 NOTES: This is a boxed Intel Pentium 4 processor with an unattached fan heatsink. Some of these processors are offered as boxed processors with an unattached fan heatsink. These are engineering samples only.

  • Page 30: Errata

    Problem: Some invalid opcodes require a ModRM byte (or other following bytes), while others do not. The invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel architecture processors, but does in the Pentium 4 processor. Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault on the Pentium 4 processor.
  • Page 31 MC2_CTL register bits to 0, uncorrectable errors should be logged in the IA32_MC2_STATUS register but no machine-check exception should be generated. Uncorrectable loads on bank 2, which would normally be logged in the IA32_MC2_STATUS register, are not logged. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 32 MCERR#. The Machine Check Exception (MCE) handler called upon assertion of MCERR# will not have any way to determine the cause of the MCE. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 33 Implication: The processor is unable to correctly report and/or recover from certain errors. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 34 Implication: The performance counters do not cascade when the FORCE_OVF bit is set. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 35 Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the page fault in the page fault handler and then restart the faulting instruction Status: For the stepping affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 36 Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the values in the reserved bits are maintained. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 37 ECC error, memory image coherency of the BWL with respect to BRL/BRIL transactions is not important. Forward progress is the primary requirement. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 38 If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software.
  • Page 39 Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 40 350 mV. The actual value could be as high as 800 mV. Implication: The PWRGOOD and TAP inputs may switch at different levels than previously documented specifications. Intel has not observed any issues in validation or simulation as a result of this erratum.
  • Page 41 FP event, the load in the microcode routine will trigger the data breakpoint resulting in a Debug Exception. Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction. Intel has not observed this erratum with any commercially available software or system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
  • Page 42 The aliasing of memory regions, a condition necessary for this erratum to occur, is ® documented as being unsupported in the IA-32 Intel Architecture Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT. However, if this erratum occurs the system may hang.
  • Page 43 (e.g. infinite number of retries). Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 44 This erratum has not been observed in commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 45 Implication: When this erratum occurs, a data breakpoint will not be captured. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 46 SSE loads are encountered. Implication: When this erratum occurs, the FP_ASSIST event may not calculate the correct number of events. As a result, performance optimization software such as Intel VTune™ Performance Analyzers may not be able to take advantage of certain scenarios.
  • Page 47 ® younger memory access. Refer to the IA-32 Intel Architecture Software Developer's Manual for the correct way to update page tables. Software that conforms to the Software Developer's Manual will operate correctly.
  • Page 48 Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 49 Space Problem: If a descriptor referenced by the selector specified for the VERR or VERW instructions is in non- ® canonical space, it may incorrectly cause a #GP fault on a processor supporting Intel Extended ® Memory 64 Technology (Intel EM64T).
  • Page 50 Extended Memory 64 Technology (Intel EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be non-zero. Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected behavior when accessing memory using the null selector.
  • Page 51 EM64T) Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack segment with a selector which references a non-canonical address will result in a #SS fault instead of a #GP fault. Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected behavior.
  • Page 52 Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating system failure. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 53 If BIOS provides only valid physical address ranges to the operating system, this erratum will not occur. Workaround: BIOS must provide valid physical address ranges to the operating system. Status: For the steppings affected, see the Summary Tables of Changes. ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...
  • Page 54 RFOs may prevent the software from making forward progress. Implication: If this erratum occurs, the software may experience a delay in making forward progress or it may hang. Intel has not observed this erratum with any commercially available software or system.
  • Page 55 Extended Memory 64 Technology (Intel EM64T) Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be non- zero. Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when accessing an LDT register using the null selector. There may be no #GP fault in response to this access.
  • Page 56 Errata R76. L-bit of the CS and LMA bit of the IA32_EFER Register May Have an Erroneous Value For One Instruction Following a Mode Transition in a ® Hyper-Threading Enabled Processor Supporting Intel Extended Memory ® 64 Technology (Intel EM64T) ®...
  • Page 57 CR2. Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not observed this erratum with any commercially available software.
  • Page 58 If a data access causes a page split across the canonical to non-canonical address space the processor may livelock which in turn would cause a system hang. Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel has not observed this erratum with any commercially available software.
  • Page 59 This behavior will only be visible when SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit. Implication: This erratum can have multiple failure symptoms including incorrect data in memory. Intel has not observed this erratum with any commercially available software.
  • Page 60 EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the upper 32 bits of the FDP value written out to memory by the FXSAVE instruction may be incorrect. Implication: This erratum may cause incorrect data to be saved into the memory.
  • Page 61 When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall for the Defer Reply transaction. Such an event will block further progress on the FSB. Implication: If this erratum occurs, the system may hang. Intel chipsets avoid the REQb conditions required to observe this erratum.
  • Page 62 As described in the IA-32 Intel Architecture Software Developer’s Manual, support for LAHF/SAHF instructions in 64-bit mode has been added to Intel EM64T processors. The CPUID feature flag may indicate that the LAHF/SAHF instructions are unavailable in 64-bit mode, even though the instructions are supported and able to be executed without an Invalid Opcode exception.
  • Page 63 Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this erratum, in a commercially available system.
  • Page 64 Access ® ® Problem: In a system supporting Intel Virtualization Technology and Intel Extended Memory 64 Technology, if the "CR8-store exiting" bit in the processor-based VM-execution control field is set and the "use TPR shadow" bit is not set, a MOV from CR8 instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit may generate an unexpected memory access.
  • Page 65 • Chip-wide power down transition is interrupted by an In-Target Probe event. Implication: Due to this erratum the processor may not recognize further STPCLK# assertions, TM1, TM2, or ® Technology. Intel has not observed this erratum with any Enhanced Intel SpeedStep commercially available software.
  • Page 66 Attempting to Use an LDT Entry when the LDTR Has Been Loaded with an Unusable Segment May Cause Unexpected Memory Accesses ® ® Problem: In a system supporting Intel EM64T and Intel Virtualization Technology when the following occur, • The LDTR is loaded during VM entry with the segment unusable bit set for the LDTR in the VMCS (Virtual-Machine Control Structure) •...
  • Page 67 The Execution of a VMPTRLD Instruction May Cause an Unexpected Memory Access ® Problem: In a system supporting Intel Virtualization Technology, executing VMPTRLD may cause a memory access to an address not referenced by the memory operand. Implication: This erratum may cause unpredictable system behavior including system hang.
  • Page 68 Implication: VM Entries and VM Exits that should fail will complete successfully in this situation. If a VM entry is to virtual-8086 mode, the base address for FS or for GS may be loaded with a value that is not consistent with that mode. Intel has not observed this erratum with any commercially available software or systems.
  • Page 69 •Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153) •L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145) Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported. Intel has not observed this erratum on any commercially available system.
  • Page 70 Reserved Bit settings in VM-exit Control Field ® Problem: Processors supporting Intel Virtualization Technology can execute VMCALL from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.
  • Page 71 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
  • Page 72 Implication: This erratum may cause system hang or unpredictable system behavior. This erratum has not been observed with commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. § ® ® Intel Pentium 4 Processor on 90 nm Process Specification Update...

  • Page 73: Specification Changes

    RESERVED to FC22 Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature.

  • Page 74: Specification Clarifications

    Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: Δ • Intel ® ® ® ® Pentium 4 Processor 670, 660, 650, 640, and 630 and Intel Pentium 4 Processor Extreme Edition Datasheet •...

  • Page 75: Documentation Changes

    4 processor documentation. Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document IA-32 Intel® Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.

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