Intel SL3VS - Celeron 633 MHz Processor Specification page 70

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C76.
Machine Check Exception may Occur When Interleaving
Code Between Different Memory Types
A small window of opportunity exists where code fetches interleaved between different memory
Problem:
types may cause a machine check exception. A complex set of micro-architectural boundary conditions is
required to expose this window.
Interleaved instruction fetches between different memory types may result in a machine check
Implication:
exception. The system may hang if machine check exceptions are disabled. Intel has not observed the
occurrence of this erratum while running commercially available applications or operating systems.
Software can avoid this erratum by placing a serializing instruction between code fetches
Workaround:
between different memory types.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C77.
Wrong ESP Register Values During a Fault in VM86 Mode
At the beginning of the IRET instruction execution in VM86 mode, the lower 16 bits of the ESP
Problem:
register are saved as the old stack value. When a fault occurs, these 16 bits are moved into the 32-bit ESP,
effectively clearing the upper 16 bits of the ESP.
This erratum has not been observed to cause any problems with commercially available
Implication:
software.
None identified
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C78.
APIC ICR Write May Cause Interrupt Not to be Sent When
ICR Delivery Bit Pending
If the APIC ICR (Interrupt Control Register) is written with a new interrupt command while the
Problem:
Delivery Status bit from a previous interrupt command is set to '1' (Send Pending), the interrupt message may
not be sent out by the processor.
This erratum will cause an interrupt message not to be sent, potentially resulting in system
Implication:
hang.
Software should always poll the Delivery Status bit in the APIC ICR and ensure that it is '0'
Workaround:
(Idle) before writing a new value to the ICR.
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
62