Intel SL3VS - Celeron 633 MHz Processor Specification page 49

C32. Misprediction in Program Flow May Cause Unexpected
Instruction Execution
To optimize performance through dynamic execution technology, the P6 architecture has the
Problem:
ability to predict program flow. In the event of a misprediction, the processor will normally clear the incorrect
prediction, adjust the EIP to the correct location, and flush out any instructions it may have fetched from the
misprediction. In circumstances where a branch misprediction occurs, the correct target of the branch has
already been opportunistically fetched into the streaming buffers, and the L2 cycle caused by the evicted
cache line is retried by the L2 cache, the processor may fail to flush out the retirement unit before the
speculative program flow is committed to a permanent state.
The results of this erratum may range from no effect to unpredictable application or OS failure.
Implication:
Manifestations of this failure may result in:
•
Unexpected values in EIP
•
Faults or traps (e.g., page faults) on instructions that do not normally cause faults
•
Faults in the middle of instructions
•
Unexplained values in registers/memory at the correct EIP
It is possible for BIOS code to contain a workaround for this erratum.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C33. Data Breakpoint Exception in a Displacement Relative Near
Call May Corrupt EIP
If a misaligned data breakpoint is programmed to the same cache line as the memory location
Problem:
where the stack push of a near call is performed and any data breakpoints are enabled, the processor will
update the stack and ESP appropriately, but may skip the code at the destination of the call. Hence, program
execution will continue with the next instruction immediately following the call, instead of the target of the call.
The failure mechanism for this erratum is that the call would not be taken; therefore,
Implication:
instructions in the called subroutine would not be executed. As a result, any code relying on the execution of
the subroutine will behave unpredictably.
Whether enabled or not, do not program a misaligned data breakpoint to the same cache line
Workaround:
on the stack where the push for the near call is performed.
For the stepping affected see the Summary of Changes at the beginning of this section.
Status:
C34. System Bus ECC Not Functional With 2:1 Ratio
If a processor is underclocked at a core frequency to system bus frequency ratio of 2:1 and
Problem:
system bus ECC is enabled, the system bus ECC detection and correction will negatively affect internal timing
dependencies.
If system bus ECC is enabled, and the processor is underclocked at a 2:1 ratio, the system
Implication:
may behave unpredictably due to these timing dependencies.
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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