Intel SL3VS - Celeron 633 MHz Processor Specification page 83

Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or
PE) registers before writing to memory early in BIOS code to clear all the global
entries from TLB.
Status: For the steppings affected, see the Summary Table of Changes.
C104. REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem:
Under certain conditions as described in the Software Developers Manual
section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon,
and P6 Family Processors" the processor performs REP MOVS or REP STOS as
fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
that cross page boundaries from WB/WC memory types to UC/WP/WT memory
types, may start using an incorrect data size or may observe memory ordering
violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the
new page memory type:
•
UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
•
WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
•
WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type
to UC, WP or WT memory type within a single REP MOVS or REP STOS
instruction that will execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes
C105. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap
Flag, bit 8) of the EFLAGS Register is set, and a #DB (Debug Exception) occurs
due to one of the following:
•
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
DR7 GD (General Detect, bit 13) being bit set;
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