Intel SL3VS - Celeron 633 MHz Processor Specification page 75

C85. Lock Data Access that Spans Two Pages May Cause the
System to Hang
Problem:
An instruction with lock data access that spans across two pages may, given
some rare internal conditions, hang the system.
Implication: When this erratum occurs, the system may hang. Intel has not observed this
erratum with any commercially available software or system.
Workaround: A lockable data access should always be aligned.
Status: For the steppings affected, see the Summary Tables of Changes.
C86. REP MOVS Operation in Fast string Mode Continues in that
Mode When Crossing into a Page with a Different Memory
Type
Problem: A fast "REP MOVS" operation will continue to be handled in fast mode when
the string operation crosses a page boundary into an Uncacheable (UC) memory
type. Also if the fast string operation crosses a page boundary into a WC
memory region, the processor will not self snoop the WC memory region. This
may eventually result in incorrect data for the WC portion of the operation if
those cache lines were previously cached as WB (through aliasing) and
modified.
Implication: String elements should be handled by the processor at the native operand size in
UC memory. In the event that the WB to WC aliasing case occurs, the end result
could vary from normal software execution to potential software failure. Intel
has not observed either aspects of this erratum in commercially available
software.
Workaround: Software operating within Intel's recommendation will not require WB and WC
memory aliased to the same physical address.
Status:
For the steppings affected, see the Summary Tables of Changes.
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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