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Errata
Errata
1.
I/O Restart in SMM May Fail after Simultaneous Machine Check
Exception (MCE).
Problem:
If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed,
and if the data for this instruction becomes corrupted, the processor will signal a
Machine Check Exception (MCE). If the instruction is directed at a device that is
powered down, the processor may also receive an assertion of SMI#. Since MCEs
have higher priority, the processor will call the MCE handler, and the SMI# assertion
will remain pending. However, upon attempting to execute the first instruction of the
MCE handler, the SMI# will be recognized and the processor will attempt to execute
the SMM handler. If the SMM handler is completed successfully, it will attempt to
restart the I/O instruction, but will not have the correct machine state, due to the call
to the MCE handler.
Implication: A simultaneous MCE and SMI# assertion may occur for one of the I/O instructions
above. The SMM handler may attempt to restart such an I/O instruction, but will have
an incorrect state due to the MCE handler call, leading to failure of the restart and
shutdown of the processor.
Workaround:
If a system implementation must support both SMM and board I/O restart, the
first thing the SMM handler code should do is check for a pending MCE. If there is an
MCE pending, the SMM handler should immediately exit via an RSM instruction and
allow the MCE handler to execute. If there is no MCE pending, the SMM handler may
proceed with its normal operation.
Status:
For the steppings affected, see the Summary Tables of Changes.
2.
MCA Registers May Contain Invalid Information If RESET# Occurs
and PWRGOOD Is Not Held Asserted
Problem:
This erratum can occur as a result either of the following events:
• PWRGOOD is de-asserted during a RESET# assertion causing internal glitches
that may result in the possibility that the MCA registers latch invalid information.
• Or during a reset sequence if the processor's power remains valid regardless of
the state of PWRGOOD, and RESET# is re-asserted before the processor has
cleared the MCA registers, the processor will begin the reset process again but
may not clear these registers.
Implication: When this erratum occurs, the information in the MCA registers may not be reliable.
Workaround:
Ensure that PWRGOOD remains asserted throughout any RESET# assertion and
that RESET# is not re-asserted while PWRGOOD is de-asserted.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
31
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