Intel SL3VS - Celeron 633 MHz Processor Specification page 24

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
NO.
650h 651h 660h
A0 A1 A0
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C65
C66
C67
16
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X
X X
X
X X X
Plans
6B1h 6B4h
A1 B1
X X NoFix FLUSH# servicing delayed
while waiting for
STARTUP_IPI in 2-way MP
systems
X X NoFix Double ECC error on read
may result in BINIT#
X X NoFix MCE due to L2 parity error
gives L1 MCACOD.LL
X X NoFix EFLAGS discrepancy on a
page fault after a
multiprocessor TLB
shootdown
X X NoFix Mixed cacheability of lock
variables is problematic in
MP systems
X X NoFix INT 1 with DR7.GD set does
not clear DR7.GD
X X NoFix Potential loss of data
coherency during MP data
ownership transfer
X X NoFix Misaligned Locked access to
APIC space results in a hang
X X NoFix Memory ordering based
synchronization may cause a
livelock condition in MP
Systems
X X NoFix Processor may assert
DRDY# on a write with no
data
Fixed Machine check exception
may occur due to improper
line eviction in the IFU
NoFix Snoop request may cause
DBSY# hang
Fixed MASKMOVQ instruction
interaction with string
operation may cause
deadlock
X X NoFix MOVD, CVTSI2SS, or
PINSRW Following Zeroing
Instruction Can Cause
Incorrect Result
ERRATA