Intel SL3VS - Celeron 633 MHz Processor Specification page 47

For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C28. MC2_STATUS MSR Has Model-Specific Error Code and
Machine Check Architecture Error Code Reversed
The Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide,
Problem:
documents that for the MC i _STATUS MSR, bits 15:0 contain the MCA (machine-check architecture) error
code fields and bits 31:16 contain the model-specific error code field. However, for the MC2_STATUS MSR,
these bits have been reversed. For the MC2_STATUS MSR, bits 15:0 contain the model-specific error code
field and bits 31:16 contain the MCA error code field.
A machine check error may be decoded incorrectly if this erratum on the MC2_STATUS MSR
Implication:
is not taken into account.
When decoding the MC2_STATUS MSR, reverse the two error fields.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C29. MOV With Debug Register Causes Debug Exception
When in V86 mode, if a MOV instruction is executed on debug registers, a general-protection
Problem:
exception (#GP) should be generated, as documented in the Intel Architecture Software Developer's Manual,
Volume 3: System Programming Guide , Section 15.2. However, in the case when the general detect enable
flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.
With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a
Implication:
MOV on debug registers in V86 mode, a debug exception will be generated instead of the expected general-
protection fault.
In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is
Workaround:
generally set and used by debuggers. The debug exception handler should check that the exception did not
occur in V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed
to the general-protection exception handler.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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