Intel SL3VS - Celeron 633 MHz Processor Specification page 59

C53. FLUSH# Servicing Delayed While Waiting for STARTUP_IPI
in 2-way MP Systems
In a 2-way MP system, if an application processor is waiting for a startup inter-processor interrupt
Problem:
(STARTUP_IPI), then it will not service a FLUSH# pin assertion until it has received the STARTUP_IPI.
After the 2-way MP initialization protocol, only one processor becomes the bootstrap processor
Implication:
(BSP). The other processor becomes a slave application processor (AP). After losing the BSP arbitration, the
AP goes into a wait loop, waiting for a STARTUP_IPI.
The BSP can wake up the AP to perform some tasks with a STARTUP_IPI, and then put it back to sleep with
an initialization inter-processor interrupt (INIT_IPI, which has the same effect as asserting INIT#), which
returns it to a wait loop. The result is a possible loss of cache coherency if the off-line processor is intended to
service a FLUSH# assertion at this point. The FLUSH# will be serviced as soon as the processor is awakened
by a STARTUP_IPI, before any other instructions are executed. Intel has not encountered any operating
systems that are affected by this erratum.
Operating system developers should take care to execute a WBINVD instruction before the
Workaround:
AP is taken off-line using an INIT_IPI.
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C54. Double ECC Error on Read May Result in BINIT#
For this erratum to occur, the following conditions must be met:
Problem:
•
Machine Check Exceptions (MCEs) must be enabled.
•
A dataless transaction (such as a write invalidate) must be occurring simultaneously with a transaction
which returns data (a normal read).
•
The read data must contain a double-bit uncorrectable ECC error.
If these conditions are met, the Celeron processor will not be able to determine which transaction was
erroneous, and instead of generating an MCE, it will generate a BINIT#.
The bus will be reinitialized in this case. However, since a double-bit uncorrectable ECC error
Implication:
occurred on the read, the MCE handler (which is normally reached on a double-bit uncorrectable ECC error
for a read) would most likely cause the same BINIT# event.
Though the ability to drive BINIT# can be disabled in the Celeron processor, which would
Workaround:
prevent the effects of this erratum, overall system behavior would not improve, since the error which would
normally cause a BINIT# would instead cause the machine to shut down. No other workaround has been
identified.
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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