Intel SL3VS - Celeron 633 MHz Processor Specification page 43

If the chipset and third party agents used with the Celeron processor do not optimize their
Workaround:
arbitration latency as described above, no action is required. For the 66 MHz Celeron processor, no action is
required.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C22. FP Data Operand Pointer May Not Be Zero After Power On or
Reset
The FP Data Operand Pointer, as specified, should be reset to zero upon power on or Reset by
Problem:
the processor. Due to this erratum, the FP Data Operand Pointer may be nonzero after power on or Reset.
Software which uses the FP Data Operand Pointer and count on its value being zero after
Implication:
power on or Reset without first executing an FINIT/FNINIT instruction will use an incorrect value, resulting in
incorrect behavior of the software.
Software should follow the recommendation in Section 8.2 of the Intel Architecture Software
Workaround:
Developer's Manual, Volume 3: System Programming Guide (Order Number 243192). This recommendation
states that if the FPU will be used, software-initialization code should execute an FINIT/FNINIT instruction
following a hardware reset. This will correctly clear the FP Data Operand Pointer to zero.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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