Intel SL3VS - Celeron 633 MHz Processor Specification page 23

NO.
650h 651h 660h
A0 A1 A0
C40 X X
C41 X X X
C42 X X X
C43 X
C44 X X X
C45 X X X
C46 X X X
C47 X X X
C48 X X X
C49 X X X
C50 X X X
C51 X X X
C52 X X X
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X X
X X
X X X
X X X
X X X X
X X
X X X X
X X X
X X X X
X X X X
X X X X
X X X
X X X X
Plans
6B1h 6B4h
A1 B1
Fixed Incorrect chunk ordering may
prevent execution of the
machine check exception
handler after BINIT#
Fixed UC write may be reordered
around a cacheable write
Fixed Resume Flag may not be
cleared after debug
exception
Fixed Internal cache protocol
violation may cause system
hang
X X NoFix GP# fault on WRMSR to
ROB_CR_BKUPTMPDR6
Fixed Machine Check Exception
may occur due to improper
line eviction in the IFU
X X NoFix Lower bits of SMRAM
SMBASE register cannot be
written with an ITP
Fixed Task switch may cause
wrong PTE and PDE access
bit to be set
X X NoFix Cross-modifying code
operations on a jump
instruction may cause a
general protection fault
Fixed Deadlock may occur due to
illegal-instruction/page-miss
combination
X X NoFix FLUSH# assertion following
STPCLK# may prevent CPU
clocks from stopping
Fixed Floating-point exception
condition may be deferred
Fixed Cache Line Reads May
Result in Eviction of Invalid
Data
ERRATA
15