Intel SL3VS - Celeron 633 MHz Processor Specification page 92

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C12. Errors in Instruction Set Reference
The following changes will be made to the Intel Architecture Software Developer's Manual, Vol 2: Instruction
Set Reference:
1. Page 3-586 "PMULUDQ—Multiply Packed Unsigned Doubleword Integers"
currently states:
66 OF F4 /r PMULUDQ xmm1, xmm2/m128
It should state:
66 0F F4 /r PMULUDQ xmm1, xmm2/m128
2 . Page A-9, Table A-3, Two-byte Opcode Map:08H-7FH (First Byte is 0FH), e ntry 2B currently
states:
MOVNTPS
Wps, Vps
MOVNTPS (66)
Wpd, Vpd
It should state:
MOVNTPS
Wps, Vps
MOVNTPD (66)
Wpd, Vpd
3 . Page A-9, Table A-3, Two-byte Opcode Map:08H-7FH (First Byte is 0FH).
Entry 3C currently states:
Blank (empty space)
It should state:
MOVNTI
4. Page A-10, Table A-3, Two-byte Opcode Map:80H-7FH (First Byte is 0FH).
Entry D7 currently states:
PMOVMSKB
Gd, Pq
PMOVMKSB (66)
Gd, Vdq
It should state:
PMOVMSKB
Gd, Pq
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