Intel SL3VS - Celeron 633 MHz Processor Specification page 21

NO.
650h 651h 660h
A0 A1 A0
C11 X X X
C12 X X X
C13 X X
C14 X X X
C15 X X
C16 X X X
C17 X
C18 X
C19 X X
C20 X X X
C21 X X
C22 X X X
C23 X X X
C24 X X X
C25 X X X
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X
X
X X X X
X
X X X X
X X X X
X X X X
X X X X
X X X X
Plans
6B1h 6B4h
A1 B1
cache line replacement
Fixed Potential early deassertion of
LOCK# during split-lock
cycles
Fixed A20M# may be inverted after
returning from and Reset
SMM
Fixed Reporting of floating-point
exception may be delayed
X X NoFix Near CALL to ESP creates
unexpected EIP address
Fixed Built-in self test always gives
nonzero result
Fixed THERMTRIP# may not be
asserted as specified
Fixed Cache state corruption in the
presence of page A/D-bit
setting and snoop traffic
Fixed Snoop cycle generates
spurious machine check
exception
Fixed MOVD/MOVQ instruction
writes to memory
prematurely
X X NoFix Memory type undefined for
nonmemory operations
Fixed Bus protocol conflict with
optimized chipsets
X X NoFix FP Data Operand Pointer
may not be zero after power
on or Reset
X X NoFix MOVD following zeroing
instruction can cause
incorrect result
X X NoFix Premature execution of a
load operation prior to
exception handler invocation
X X NoFix Read portion of RMW
instruction may execute
twice
ERRATA
13