Intel SL3VS - Celeron 633 MHz Processor Specification page 84

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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the DR6 BS (Single Step, bit 14) flag may be incorrectly set.
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes
C106. Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this
erratum, if execution of the ENTER instruction results in a fault, the dynamic
storage area of the resultant stack frame may contain unexpected values (i.e.
residual stack data as a result of processing the fault).
Data in the created stack frame may be altered following a fault on the ENTER
Implication:
instruction. Please refer to "Procedure Calls For Block-Structured Languages" in IA-32
Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information
on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3.
Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0.
Intel has not observed this erratum on any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes
C107: Unaligned Accesses to Paging Structures May Cause the
Processor to Hang
When an unaligned access is performed on paging structure entries, accessing a portion
Problem:
of two different entries simultaneously, the processor may live lock.
When this erratum occurs, the processor may live lock causing a system hang.
Implication:
Do not perform unaligned accesses on paging structure entries.
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
76
INT1 instruction;
Code breakpoint