Intel SL3VS - Celeron 633 MHz Processor Specification page 22

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
NO.
650h 651h 660h
A0 A1 A0
C26 X X X
C27 X X X
C28 X X X
C29 X X X
C30 X X X
C31 X X
C32 X X X
C33 X X X
C34 X X X
C35 X X X
C36 X X X
C37 X X X
C38 X X X
C39 X X X
14
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X
X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X
X X X X
X X X X
X X X X
X X X
Plans
6B1h 6B4h
A1 B1
Fixed Test pin must be high during
power up
X X Fixed Intervening writeback may
occur during locked
transaction
X X NoFix MC2_STATUS MSR has
model-specific error code
and machine check
architecture error code
reversed
X X NoFix MOV with debug register
causes debug exception
X X NoFix Upper four PAT entries not
usable with Mode B or Mode
C paging
Fixed Incorrect memory type may
be used when MTRRs are
disabled
Fixed Misprediction in program
flow may cause unexpected
instruction execution
X X NoFix Data Breakpoint Exception in
a displacement relative near
call may corrupt EIP
X X NoFix System bus ECC not
functional with 2:1 ratio
X X Fixed Fault on REP CMPS/SCAS
operation may cause
incorrect EIP
NoFix RDMSR and WRMSR to
invalid MSR address may not
cause GP fault
NoFix SYSENTER/SYSEXIT
instructions can implicitly
load "null segment selector"
to SS and CS registers
NoFix PRELOAD followed by
EXTEST does not load
boundary scan data
Fixed Far jump to new TSS with D-
bit cleared may cause
system hang
ERRATA