Intel SL3VS - Celeron 633 MHz Processor Specification page 98

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
C17. Omission of Dependency Between BTM and LBR
The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 15 , Section
5.3, on page 15-15 currently states:
15.5.3. Monitoring Branches, Exceptions, and Interrupts (Pentium
4 and Intel Xeon Processors)
When the LBR flag in the IA32_DEBUGCTL MSR is set, the processor automatically begins
recording branch records for taken branches, interrupts, and exceptions (except for debug
exceptions)
in the LBR stack MSRs.
When the processor generates a debug exception (#DB), it automatically clears the LBR flag
before executing the exception handler, but does not touch the LBR stack MSRs. The branch
records for the last four taken branches, interrupts, and/or exceptions are thus retained for anal-ysis
by the debugger program.
The debugger can use the linear addresses in the LBR stack to reset breakpoints in the break-point-
address registers (DR0 through DR3), allowing a backward trace from the manifestation
of a particular bug toward its source.
Before resuming program execution from a debug-exception handler, the handler must set the
LBR flag again to re-enable last branch recording.
It should state:
15.5.3. Monitoring Branches, Exceptions, and Interrupts (Pentium
4 and Intel Xeon Processors)
When the LBR flag in the IA32_DEBUGCTL MSR is set, the processor automatically begins
recording branch records for taken branches, interrupts, and exceptions (except for debug
exceptions)
in the LBR stack MSRs.
When the processsor generates a debug exception (#DB), it automatically clears the LBR flag
before executing the exception handler. This action does not clear previously stored LBR stack
MSRs. The branch record for the last four taken branches, interrupts and/or exceptions are retained
for analysis.
A debugger can use the linear addresses in the LBR stack to reset breakpoints in the break-point
address registers (DR0 through DR3). This allows a backward trace from the manifestation of a
particular bug toward its source.
If the LBR flag is cleared and TR flag in the IA32_DEBUGCTLTR MSR remains set, the processor
will continue to update LBR stack MSRs. This is because BTM information must be generated from
entries in the LBR stack (see 14.5.5). A #DB does not automatically clear the TR flag.
90