Intel SL3VS - Celeron 633 MHz Processor Specification page 57

C49. Deadlock May Occur Due To Illegal-Instruction/Page-Miss
Combination
Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space;
Problem:
however some byte combinations remain undefined and are considered illegal instructions. Intel processors
detect the attempted execution of illegal instructions and signal an exception. This exception is handled by
the operating system and/or application software.
Under a complex set of internal and external conditions involving illegal instructions, a deadlock may occur
within the processor. The necessary conditions for the deadlock involve:
1. The illegal instruction is executed.
2.
Two page table walks occur within a narrow timing window coincident with the illegal instruction.
The illegal instructions involved in this erratum are unusual and invalid byte combinations that
Implication:
are not useful to application software or operating systems. These combinations are not normally generated in
the course of software programming, nor are such sequences known by Intel to be generated in commercially
available software and tools. Development tools (compilers, assemblers) do not generate this type of code
sequence, and will normally flag such a sequence as an error. If this erratum occurs, the processor deadlock
condition will occur and result in a system hang. Code execution cannot continue without a system RESET.
None identified
Workaround:
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C50. FLUSH# Assertion Following STPCLK# May Prevent CPU
Clocks From Stopping
If FLUSH# is asserted after STPCLK# is asserted, the cache flush operation will not occur until
Problem:
after STPCLK# is de-asserted. Furthermore, the pending flush will prevent the processor from entering the
Sleep state, since the flush operation must complete prior to the processor entering the Sleep state.
Following SLP# assertion, processor power dissipation may be higher than expected.
Implication:
Furthermore, if the source to the processor's input bus clock (BCLK) is removed, normally resulting in a
transition to the Deep Sleep state, the processor may shutdown improperly. The ensuing attempt to wake up
the processor will result in unpredictable behavior and may cause the system to hang.
For systems that use the FLUSH# input signal and Deep Sleep state of the processor, ensure
Workaround:
that FLUSH# is not asserted while STPCLK# is asserted.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
49