Intel SL3VS - Celeron 633 MHz Processor Specification page 93

PMOVMSKB (66)
Gd, Vdq
5 . Page A-10, Table A-3, Two-byte Opcode Map:80H-7FH (First Byte is 0FH).
Entry F7 currently states:
MASKMOVQ
Ppi, Qpi
MASKMOVQU (66)
Vdq, Wdq
It should state:
MASKMOVQ
Ppi, Qpi
MASKMOVDQU (66)
Vdq, Wdq
6. Page A-11, Table A-3 , Two-byte Opcode Map:88H-7FH (First Byte is 0FH).
The title table currently states:
Table A-3. Two-byte Opcode Map:88H-7FH (First Byte is FFH)
It should state:
Table A-3. Two-byte Opcode Map:88H-7FH (First Byte is 0FH)
7. Page A-11, Table A-3 , Two-byte Opcode Map:88H-7FH (First Byte is 0FH).
Entry FB currently states:
PSUBD
Pq, Qq
PSUBD (66)
Vdq, Wdq
It should state:
PSUBQ
Pq, Qq
PSUBQ (66)
Vdq, Wdq
8. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.).
Entry PMADD currently states:
PMADD – Packed Multiply add
It should state:
PMADDWD – Packed Multiply add
9. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.).
Entry PMULH currently states:
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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