Intel SL3VS - Celeron 633 MHz Processor Specification page 91

C9. 0x33 Opcode
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Appendix A, Table A-2,
the opcode corresponding to 0x33 currently states:
Gb, Ev
It should state:
Gv, Ev
Also, Page 3-791, XOR-Logical Exclusive OR, the two entries for opcode 33 currently state:
Opcode Instruction
33 /r XOR r16,r/m16
33 /r XOR r32,r/m32
It should state:
Opcode
33 /r r16 XOR r/m16
33 /r r32 XOR r/m32
C10. Incorrect Information for SLDT
In the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, the
opcode/Instruction/Description table for SLDT currently states "SLDT r/m32 Store segment selector from
LDTR in low-order 16 bits of r/m32 " but should instead list "SLDT r32 Store segment selector from LDTR in
low-order 16 bits of r32 ."
C11. LGDT/LIDT Instruction Information Correction
In the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, the sentence in the
LGDT/LIDT instruction section currently states:
"See 'SFENCE -- Store Fence' in this chapter for information on storing the contents of the GDTR
and IDTR."
It should state:
"See 'SGDT/SIDT' in this chapter for information on storing the contents of the GDTR and IDTR."
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
Description
r8 XOR r/m8
r8 XOR r/m8
Instruction
r8 XOR r/m8
r8 XOR r/m8
Description
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