Intel SL3VS - Celeron 633 MHz Processor Specification page 94

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
PMULH – Packed multiplication
It should state:
PMULHW – Packed multiplication, store high word
10. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.).
Add instruction PMULHUW :
PMULHUW – Packed multiplication, store high word (unsigned)
mmxreg2 to mmxreg1
memory to mmxreg
11. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.).
Entry PMULL currently states:
PMULL – Packed multiplication
It should state:
PMULLW – Packed multiplication, store low word
12 . Page B-40, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction.
Entry PMADD currently states:
PMADD – Packed multiply add
It should state:
PMADDWD – Packed multiply add
13. Page B-41, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction.
Entry PMULH currently states:
PMULH – Packed multiplication
It should state:
PMULHW – Packed multiplication, store high word
14. Page B-41, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction.
Add instruction PMULHUW:
PMULHUW – Packed multiplication, store high word (unsigned)
xmmreg2 to xmmreg1
memory to xmmreg
86
0000 1111: 1110 0100: 11 mmxreg1 mmxreg2
0000 1111: 1110 0100: mod mmxreg r/m
0110 0110 : 0000 1111 : 11110 0100 : 11 xmmreg1 xmmreg2
0110 0110 : 0000 1111 : 1110 0100 : mod xmmreg r/m