Intel SL3VS - Celeron 633 MHz Processor Specification page 65

For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C66. MASKMOVQ Instruction Interaction with String Operation
May Cause Deadlock
Under the following scenario, combined with a specific alignment of internal events, the processor
Problem:
may enter a deadlock condition:
1. A store operation completes, leaving a write-combining (WC) buffer partially filled.
2. The target of a subsequent MASKMOVQ instruction is split across a cache line.
3. The data in (2) above results in a hit to the data in the WC buffer in (1).
If this erratum occurs, the processor deadlock condition will occur and result in a system hang.
Implication:
Code execution cannot continue without a system RESET.
It is possible for BIOS code to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C67. MOVD, CVTSI2SS, or PINSRW Following Zeroing Instruction
Can Cause Incorrect Result
Problem: An incorrect result may be calculated after the following circumstances occur:
1. A register has been zeroed with either a SUB reg, reg instruction, or an XOR reg, reg instruction.
2. A value is moved with sign extension into the same register's lower 16 bits; or a signed integer
multiply is performed to the same register's lower 16 bits.
3. The register is then copied to an MMX™ technology register using the MOVD, or converted to
single precision floating-point and moved to an MMX technology register using the CVTSI2SS instruction prior
to any other operations on the sign-extended value, or inserted into an MMX™ technology register using the
PINSRW instruction.
Specifically, the sign may be incorrectly extended into bits 16-31 of the MMX technology register. In the case
of the PINSRW instruction, a non-zero value could be loaded into the MMX™ technology register. This
erratum only affects the MMX™ technology register.
This erratum only occurs when the following three steps occur in the order shown. This erratum may occur
with up to 63 (39 for Pre-CPUID 0x6BX) intervening instructions that do not modify the sign-extended value
between steps 2 and 3.
1. XOR EAX, EAX
or SUB EAX, EAX
2. MOVSX AX, BL
or MOVSX AX, byte ptr <memory address> or MOVSX AX, BX
or MOVSX AX, word ptr <memory address> or IMUL BL (AX implicit, opcode F6 /5)
or IMUL byte ptr <memory address> (AX implicit, opcode F6 /5) or IMUL AX, BX (opcode 0F AF /r)
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
57