Intel SL3VS - Celeron 633 MHz Processor Specification page 99

C18. I/O Permissions Bitmap Base Addy > 0xDFFF Does not
Cause #GP(0) Fault
The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture, page 12-6, section 12.5.2, last
paragraph currently states:
If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O
permission map, and all I/O instructions generate exceptions when the CPL is greater than the
current IOPL. The I/O bit map base address must be less than or equal to DFFFH.
It should state:
If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O
permission map, and all I/O instructions generate exceptions when the CPL is greater than the
current IOPL.
C19. Wrong Field Width for MINSS and MAXSS
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Section 3.2 Instruction
Reference under "MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value" page 3-
415 currently states:
DEST[63-0] .IF ((DEST[31-0] = 0.0) AND (SRC[31-0] = 0.0)) THEN SRC[31-0]
It should state:
DEST[31-0] .IF ((DEST[31-0] = 0.0) AND (SRC[31-0] = 0.0)) THEN SRC[31-0]
The Intel Architecture Software Developer's Manual, Vol 2 Section 3.2 Instruction Reference under title
"MINSS—Return Minimum Scalar Single-Precision floating-Point Value" page 3-428 currently states:
DEST[63-0] .IF ((DEST[31-0] = 0.0) AND (SRC[31-0] = 0.0)) THEN SRC[31-0]
It should state:
DEST[31-0] .IF ((DEST[31-0] = 0.0) AND (SRC[31-0] = 0.0)) THEN SRC[31-0]
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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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