Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification
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Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification

Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification

64-bit intel xeon processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update
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64-bit Intel
with 800 MHz System Bus (1 MB
and 2 MB L2 Cache Versions)
Specification Update
June 2006
®
Notice: The 64-bit Intel
Xeon
versions) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are documented in this
specification update.
®
®
Xeon
Processor
®
processor with 800 MHz system bus (1 MB and 2 MB L2 cache
Document Number: 302402-022

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Summary of Contents for Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor

  • Page 1 Specification Update June 2006 ® ® Notice: The 64-bit Intel Xeon processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
  • Page 2 INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.

  • Page 3: Table Of Contents

    Identification Information ....................7 Summary Table of Changes..................... 12 Errata..........................19 Specification Changes...................... 44 Specification Clarifications ....................45 Documentation Changes....................46 ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 4 ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...

  • Page 5: Revision History

    • Added errata S78-S79; added additional text to “Mixed Steppings In January 2005 DP Systems” chapter. -009 • Added 2 MB L2 cache version of the 64-bit Intel® Xeon® processor February 2005 with 800 MHz system bus; added errata S80-S81; added S-spec numbers SL7ZC, SL7ZD, SL7ZE, and SL7ZF to...

  • Page 6: Preface

    Preface Preface This document is an update to the specifications contained in the following documents: ® ® 1. 64-bit Intel Xeon Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://developer/design/xeon/datashts/306249.htm ® ® 2. Intel Xeon Processor with 800 MHz System Bus Datasheet (Document Number 302355) Link: http://developer/design/xeon/datashts/302355.htm...

  • Page 7: Identification Information

    FPO – Serial Number Text Line1 Text Line2 Text Line3 ® ® The 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 cache versions) can be identified by the following values: ® ® 64-bit Intel...
  • Page 8 Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the Intel Processor Identification and the CPUID Instruction Application Note (AP-485) for further information on the CPUID instruction.
  • Page 9 2. These parts have Thermal Monitor 2 (TM2) feature enabled. For D-0 stepping, TM2 is enabled on 3.40 GHz and above, but it is NOT supported. ® 3. These parts are enabled for Enhanced Intel SpeedStep Technology (EIST). 4. These parts are enabled for Enhanced Halt State (C1E).

  • Page 10: Mixed Steppings In Dp Systems

    Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with 800 MHz system bus as well as mixed steppings of the 64-bit Intel Xeon processor with 2 MB L2 cache. The following list and processor matrix describes the requirements to support mixed steppings: •...
  • Page 11 Identification Information ® ® Table 3. DP Platform Population Matrix for the 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) FC-PGA4 Package Processor Signature / Core 0F34h / D-0 0F41h / E-0...

  • Page 12: Summary Table Of Changes

    The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
  • Page 13 ® AC = Intel Celeron processor in 478-pin package ® ® The Specification Updates for the Pentium processor, Pentium Pro processor, and other Intel products do not use this convention. Errata (Sheet 1 of 5) D-0/ E-0/ G-1/ N-0/ R-0/...
  • Page 14 Writing the Echo TPR disable bit in IA32_MISC_ENABLE may cause a #GP fault Fixed Incorrect access controls to MSR_LASTBRANCH_0_FROM_LIP MSR registers ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 15 Intel® Extended Memory 64 Technology (Intel® EM64T) Fixed LDT descriptor which crosses 16 bit boundary access does not cause a #GP fault on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Fixed Upper reserved bits are incorrectly checked while loading PDPTR's on a processor supporting Intel®...
  • Page 16 Intel® Extended Memory 64 Technology (Intel® EM64T) Fixed The base of an LDT (Local Descriptor Table) register may be non-zero on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Fixed Unaligned Page-Directory-Pointer (PDPTR) Base with 32-bit mode PAE (Page Address Extension) paging may cause...
  • Page 17 No Fix Debug Status Register (DR6) Breakpoint Condition Detected Flags May be Set Incorrectly. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...

  • Page 18: Specification Changes

    None for this revision of the Specification Update. Documentation Changes DOCUMENTATION CHANGES None for this revision of the Specification Update. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...

  • Page 19: Errata

    Problem: invalid opcode 0FFFh did not require a ModRM in previous generation microprocessors such as Pentium II or Pentium III processors, but it is required in the Intel Xeon processor. Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault on the Intel Xeon processor.
  • Page 20 IA32_MC0_STATUS register records this event as multiple errors, i.e., the valid error bit and the overflow error bit are both set indicating that a machine check error ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 21 Stop Grant State and finally issue a Stop Grant Acknowledge special cycle to the bus. If an uncorrectable error is generated during the Stop Grant process it is possible for the Stop Grant ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 22 The performance counters do not cascade when the FORCE_OVF bit is set. Implication: Workaround: None at this time. For the steppings affected, see the Summary Table of Changes. Status: ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 23 Alternately, ensure that the page fault handler restarts program execution at the faulting instruction after correcting the paging problem. For the steppings affected, see the Summary Table of Changes. Status: ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 24 STPCLK# is not asserted at a 12.5% duty cycle. For the steppings affected, see the Summary Table of Changes. Status: ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 25 If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the Problem: processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None at this time.
  • Page 26 Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop making forward progress. Intel has not observed this erratum with any commercially available software. None at this time.
  • Page 27 STPCLK# assertion. When this erratum occurs in an HT Technology enabled system, it may cause a system hang. Implication: ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 28 The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as ® being unsupported in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3, Section 10.12.4, Programming the PAT. However, if this erratum occurs the system may hang The pages should not be mapped as either UC or WC and WB at the same time.
  • Page 29 This erratum has not been observed with commercially available software. None at this time. Workaround: Status: For the steppings affected, see the Summary Table of Changes. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 30 ® younger memory access. Refer to the IA-32 Intel Architecture Software Developer’s Manual for the correct way to update page tables. Software that conforms to the Software Developer's Manual will operate correctly.
  • Page 31 ® supporting Intel Extended Memory 64 Technology (Intel EM64T) In IA-32e mode of the Intel EM64T processor, the upper 32 bits of the FDP value written out to Problem: memory by the FXSAVE instruction may be incorrect. Implication: This erratum may cause incorrect data to be saved into the memory.
  • Page 32 Extended Memory 64 Technology (Intel EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be non-zero. Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected behavior when accessing memory using the null selector.
  • Page 33 ® (Intel EM64T) In IA-32 and IA-32e mode of the Intel processor, upper reserved bits are incorrectly checked while Problem: loading PDPTR's, allowing software to set the reserved bits. Operating system or driver software is able to set the reserved bits which may result in an Implication: unexpected system behavior.
  • Page 34 It is possible for the BIOS to contain a workaround for this erratum. Workaround: For the steppings affected, see the Summary Table of Changes. Status: ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 35 Technology (Intel EM64T) Problem: Processors which support Intel EM64T always perform canonical address checks before accessing memory. SYSENTER or SYSEXIT instructions may check an incorrect address. Implication: Due to this erratum, an unexpected #GP fault may occur, or a reference to a non-canonical address without a #GP fault may occur.
  • Page 36 Implication: Due to this erratum, the system may livelock until some external event interrupts the locked update. Intel has not observed this erratum with any commercially available software. Workaround: None at this time. For the steppings affected, see the Summary Table of Changes.
  • Page 37 Intel Extended Memory 64 Technology (Intel EM64T) Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be non-zero. Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when accessing an LDT register using the null selector.
  • Page 38 CR2. Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not observed this erratum with any commercially available software.
  • Page 39 ® Extended Memory 64 Technology (Intel EM64T) In IA-32e mode using Intel EM64T-enabled processors, a REP LOSDB or an REP LODSD or an Problem: REP LODSQ instruction executed with the register RCX >= 2^32 may fail to complete execution causing a system hang. Additionally, there may be no #GP fault due to the non-canonical address in the RSI register.
  • Page 40 When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall for the Defer Reply transaction. Such an event will block further progress on the FSB. Implication: If this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available system. None identified.
  • Page 41 Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this erratum, in a commercially available system. Workaround: None identified.
  • Page 42 The highest priority error will be logged and signaled if enabled, but the overflow bit in the Implication: IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set. None identified. Workaround: Status: No Fix. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...
  • Page 43 Due to this erratum the breakpoint condition detected flags may be set incorrectly. Implication: Workaround: None identified. No Fix. Status: ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update...

  • Page 44: Specification Changes

    ® ® 2. Intel Xeon Processor with 800 MHz System Bus Datasheet (Document Number 302355) Link: http://developer/design/xeon/datashts/302355.htm All Specification Changes will be incorporated into a future version of the appropriate Intel Xeon processor documentation. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus...

  • Page 45: Specification Clarifications

    ® ® 2. Intel Xeon Processor with 800 MHz System Bus Datasheet (Document Number 302355) Link: http://developer/design/xeon/datashts/302355.htm All Specification Clarifications will be incorporated into a future version of the appropriate Intel Xeon processor documentation. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus...

  • Page 46: Documentation Changes

    ® ® 2. Intel Xeon Processor with 800 MHz System Bus Datasheet (Document Number 302355) Link: http://developer/design/xeon/datashts/302355.htm All Documentation Changes will be incorporated into a future version of the appropriate Intel Xeon processor documentation. ® ® 64-bit Intel Xeon Processor with 800 MHz System Bus...

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