Intel SL3VS - Celeron 633 MHz Processor Specification page 67

*Note: MOV EAX, EAX is used here in a generic sense. Again, EAX can be substituted with any 32-bit
register.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
C68.
Snoop Probe During FLUSH# Could Cause L2 to be Left in
Shared State.
During a L2 FLUSH operation using the FLUSH# pin, it is possible that a read request from a bus
Problem:
agent or other processor to a valid line will leave the line in the Shared state (S) instead of the Invalid state (I)
as expected after flush operation. Before the FLUSH operation is completed, another snoop request to
invalidate the line from another agent or processor could be ignored, again leaving the line in the Shared
state.
Current desktop and mid range server systems have no mechanism to assert the flush pin and
Implication:
hence are not affected by this errata. A high end server system that does not suppress snoop traffic before
the assertion of the FLUSH# pin may cause a line to be left in an incorrect cache state.
Affected systems (those capable of asserting the FLUSH# pin) should prevent snoop activity
Workaround:
on the front side bus until invalidation is completed after asserting FLUSH#, or use a WBINVD instruction
instead of asserting the FLUSH# pin in order to flush the cache.
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
C69.
Livelock May Occur Due to IFU Line Eviction
Following the conditions outlined for erratum C63, if the instruction that is currently being executed
Problem:
from the evicted line must be restarted by the IFU, and the IFU receives another partial hit on a previously
executed (but not as yet completed) store that is resident in the store buffer, then a livelock may occur.
If this erratum occurs, the processor will hang in a live lock-situation, and the system will
Implication:
require a reset to continue normal operation.
None identified
Workaround:
For the steppings affected, see the Summary of Changes at the beginning of this section.
Status:
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
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