Intel SL3VS - Celeron 633 MHz Processor Specification page 42

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INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
3. The unmasked floating-point exception case only occurs if the store is the first MMX technology instruction
in an MMX technology routine and the previous floating-point routine exited with an unmasked floating-
point exception pending. Again, for a store to be executed as the first MMX instruction in an MMX
technology routine following a floating-point routine, the software would be implementing instruction level
intermixing of floating-point and MMX instructions. Intel does not recommend this practice.
Device Not Available (DNA) exceptions occur naturally when a task switch is made between two tasks that
use either floating-point instructions and/or MMX instructions. For this erratum, in the event of the DNA
exception, data from the prior task may be temporarily stored to the present task's program state.
Do not use MMX instructions to manipulate semaphores for multiprocessor synchronization.
Workaround:
Do not use MOVD/MOVQ instructions to write directly to I/O devices if doing so triggers user visible side
effects. An OS can prevent old data from being stored to a new task's program state by cleansing the FPU
explicitly after every task switch. Follow Intel's recommended programming paradigms in the Intel Architecture
Developer's Optimization Manual for writing MMX technology programs. Specifically, do not mix floating-point
and MMX instructions. When transitioning to new a MMX technology routine, begin with an instruction that
does not depend on the prior state of either the MMX technology registers or the floating-point registers, such
as a load or PXOR mm0, mm0. Be sure that the FP TOS is clear before using MMX instructions.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C20. Memory Type Undefined for Nonmemory Operations
The Memory Type field for nonmemory transactions such as I/O and Special Cycles are
Problem:
undefined. Although the Memory Type attribute for nonmemory operations logically should (and usually does)
manifest itself as UC, this feature is not designed into the implementation and is therefore inconsistent.
Bus agents may decode a non-UC memory type for nonmemory bus transactions.
Implication:
Bus agents must consider transaction type to determine the validity of the Memory Type field
Workaround:
for a transaction.
For the steppings affected see the Summary of Changes at the beginning of this section.
Status:
C21. Bus Protocol Conflict With Optimized Chipsets
A "dead" turnaround cycle with no agent driving the address, address parity, request command, or
Problem:
request parity signals must occur between the processor driving these signals and the chipset driving them
after asserting BPRI#. The Celeron processor does not follow this protocol. Thus, if a system uses a chipset
or third party agent which optimizes its arbitration latency (reducing it to 2 clocks when it observes an active
(low) ADS# signal and an inactive (high) LOCK# signal on the same clock that BPRI# is asserted (driven
low)), the Celeron processor may cause bus contention during an unlocked bus exchange.
This violation of the bus exchange protocol when using a reduced arbitration latency may
Implication:
cause a system-level setup timing violation on the address, address parity, request command, or request
parity signals on the system bus. This may result in a system hang or assertion of the AERR# signal, causing
an attempted corrective action or shutdown of the system, as the system hardware and software dictate. The
possibility of failure due to the contention caused by this erratum may be increased due to the processor's
internal active pull-up of these signals on the clock after the signals are no longer being driven by the
processor.
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