Intel SL3VS - Celeron 633 MHz Processor Specification page 89

It should state:
"If FOP code compatibility mode is enabled, the FOP is defined as it
has always been in previous IA32 implementations (always defined as the FOP
of the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE).
If FOP code compatibility mode is disabled (default), FOP is only valid if
the last non-transparent FP instruction executed before a
FSAVE/FSTENV/FXSAVE had an unmasked exception."
C5. FCOS, FPTAN, FSIN, and FSINCOS Trigonometric Domain
NOT correct.
The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Section 3.2
"INSTRUCTION REFERENCE" FCOS, FPTAN, FSIN, and FSINCOS trigonometric domain for C2 is incorrect.
Under the FPU Flags affected, C2 currently states:
C2 Set to 1 if source operand is outside the range -2
It should state:
C2 Set to 1 if outside range -2
C6. Incorrect Description of stack
The IA-32 Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture Chapter 6, Section
6.2 paragraph 2, labeled "STACK" currently states:
The next available memory location on the stack is called the top of stack. At any given time, the
stack pointer (contained in the ESP register) gives the address (that is the offset from the base of
the SS segment) of the top of the stack.
This paragraph is incorrect and will be removed from the section listed above.
®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
63
to +2
63 63
<source operand <+2 ; otherwise, set to 0.
63
; otherwise, cleared to 0.
81