Intel SL3VS - Celeron 633 MHz Processor Specification page 28

®
INTEL CELERON® PROCESSOR SPECIFICATION UPDATE
NO.
650h 651h 660h
A0 A1 A0
C101 X X X
C102 X X X
C103 X X X
C104 X X X
C105 X X X
C106 X X X
C107 X X X
C108 X X X
C109 X X X
C110 X X X
C111 X X X
20
Summary of Errata
CPUID/Stepping
665h 683h 686h 68Ah
B0 B0 C0 D0
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
X X X
X
Plans
6B1h 6B4h
A1 B1
Have Not Occurred
Using 2M/4M Pages When
A20M# Is Asserted May
X NoFix
X
Result in Incorrect Address
Translations
Values for LBR/BTS/BTM will
X NoFix be Incorrect after an Exit
X
from SMM
INIT Does Not Clear Global
X NoFix
X
Entries in the TLB
REP MOVS/STOS Executing
with Fast Strings Enabled
and Crossing Page
Boundaries with Inconsistent
X NoFix
X
Memory Types may use an
Incorrect Data Size or Lead
to Memory-Ordering
Violations
The BS Flag in DR6 May be
X NoFix Set for Non-Single-Step #DB
X
Exception
Fault on ENTER Instruction
X NoFix May Result in Unexpected
X
Values on Stack Frame
Unaligned Accesses to
Paging Structures May
X NoFix
X
Cause the Processor to
Hang
INVLPG Operation for Large
(2M/4M) Pages May be
X NoFix
X
Incomplete under Certain
Conditions
Page Access Bit May be Set
X NoFix Prior to Signaling a Code
X
Segment Limit Fault
EFLAGS, CR0, CR4 and the
X NoFix EXF4 Signal May be
X
Incorrect after Shutdown
Performance Monitoring
Event
X NoFix FP_MMX_TRANS_TO_MMX
X
May Not Count Some
Transitions
ERRATA