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6.7.
VIDEO CHARACTER INSERTER CIRCUIT DESCRIPTION
TECHNICAL DESCRIPTION
At VSYNC, the MCU releases the reset to U7b, enabling the VITC reader
circuitry. The first VITC data bit turns on U7a, which releases the reset to
CRC detector U1 and U3. A phase locked loop consisting of VCO U13,
and U12, U17, and U18, provides an 8 times bit rate clock to divider U11,
which generates a series of timing pulses at the VITC bit rate (1.78977
MHz for NTSC, 1.8125 MHz for PAL). Each positive going transition of the
VITC data re-synchronizes the divider so that the VITC recovery clock at
U5 pin 13 occurs in the middle of each bit.
Inverted VITC data is shifted into U3 which calculates the cyclic
redundancy check (CRC) word for the recovered data. Valid CRC and 90
bits of code, detected by U1, clocks U7b on, disabling the VITC clock and
generating a VITC RDY signal to the MCU. The MCU unloads the VITC
data through switch U17, located on the main circuit board.
The 631 character generator is a microcontroller based module functionally
divided into the following hardware subsystems:
1. Microcontroller & I/O
2. Sync Separator/Video processing
3. Character Generator logic
4. Character Generator Keyer
VIDEO IN
EV-COM
Inter-module
serial comm.
Figure 6-12: 631 Module Block Diagram
The microcontroller, sync separator and video processing circuits are
contained on the main circuit card (6120).
circuitry is contained on a separate sub-module (6231) which plugs into the
Model 4025 Film Footage Encoder Manual
SERIAL I/O
VIDEO + CHAR OUT
MAIN PROCESSOR
CHAR. GENERATOR
FORMATING SWITCHES
The character generator
Page 6-21
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