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6.8.
VITC GENERATOR AND CHARACTER GENERATOR CIRCUIT DESCRIPTION
TECHNICAL DESCRIPTION
The 6231 video keyer submodule is used for both the VITC generator and
for the character generator in the 4025. This submodule can be used with
either the 6150 or 6120 base processor boards, as needed. Video in and
out, and the MCU address and data bus are fed up the header from the
main board. The majority of the logic for the VITC and character generator
functions is contained in a programmable logic device (LCA) U7.
program is loaded from EPROM U8 on power up. Jumper JP3, located at
the front of the board determines whether the VITC generator configuration
or the character generator configuration will be loaded.
generator configuration also has the ability to display some rudimentary
characters, although this is not its primary function.
6.8.1. VITC Generator Logic (6231-32) & (6231-33)
The VITC bit rate for PAL and NTSC are generated by two crystal
controlled oscillators consisting of XT1 and U14a (for PAL) and XT2 and
U14b (for NTSC), and associated components. The NTSC/PAL control
signal (NP test point) controls which crystal oscillator is active. Jumper JP8
controls whether the VITC oscillator, or character oscillator is present on
the DCLK test point. Set JP8 to the V position to measure the VITC
frequency. The oscillator output is buffered by U14c and may be measured
at the DCLK test point when jumper JP8 is in the V position.
controls whether the PAL or NTSC oscillator is active. Set JP9 to the P
position to measure the PAL oscillator, position N to measure the NTSC
oscillator. Both JP8 and JP9 should be set to the A position for normal
operation. The frequency of 14.31818 MHz for NTSC, or 14.5 MHz for PAL
is 8 times the VITC bit rate. The VITC oscillator is divided by 8 in the LCA
to generate the correct VITC bit rate.
The starting position of the VITC on the line is fixed internally in the LCA
such that the first bit of code is 10.5 µsec (11.5 µsec for PAL) after the
leading edge of horizontal sync.
Once per field, the MCU loads the VITC bit pattern for a particular line into
static RAM U9. It is thus possible for the 4025 to generate different VITC
data for individual video lines. In practice, the 4025 will generate one line
pair for the primary VITC generator and another for the secondary line pair.
On lines where VITC is enabled, the LCA accesses the static RAM and
fetches the VITC data one byte (8 bits) at a time. The VITC sync bits and
cyclic redundancy check byte (CRC) are generated internally in the LCA
and inserted into the VITC bit stream in the appropriate place. The VITC
data is clocked out of the LCA on the KEYFILL output ( U7 pin 7) and into
buffer U8a. The VITC keyer is controlled by the KEY signal, generated in
the LCA (U7 pin 6). The data is clocked out of the LCA with the VITC
clock, so that the bit width is not dependent on propagation delays in the
LCA.
VITC bits are shaped by U6b and associated components, and
presented to the video keyer when the VITC/CHAR signal is LOW.
Model 4025 Film Footage Encoder Manual
Its
The VITC
Jumper JP9
Page 6-23
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