Jtag Port - NXP Semiconductors QorIQ LS1028A Reference Manual

Configuration signal
CFG_XSPI_MAP SW1[8]
The NAND and NOR device selection is based on the RCW_BOOT_SRC settings. Refer
to System configuration

2.14 JTAG port

The JTAG port provides access to the processor using a standard 10-pin Arm Cortex
JTAG connector for debugging purposes. The following figure shows the LS1028ARDB
JTAG architecture.
LS1028
TMS
TCK
OVDD
TDO
(1.8V)
TDI
TBSCAN_EN_B
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
Table 2-12. XSPI configuration
DIP switch CPLD register
BRDCFG0[6]
for more details.
1V8 1V8 1V8 1V8
10K
(4x)
DUT_TMS
DUT_TCK
DUT_TDO
DUT_TDI
1V8
10K
Figure 2-15. JTAG architecture
Confidential Proprietary
Chapter 2 LS1028ARDB Functional Description
Description
Bit value XSPI_A_CS
0
0 Devices (Dev
0, Dev 1)
1 Emulator
PIN-M-180-1.27mm
XSPI_A_CS Description
1
Emulator Normal
Devices (Dev Boot from
0, Dev 1) QSPI
emulator,
program
default flash
memory
1V8
100 W
1/4W
2 1
ARM
4 3
JTAG
6 5
Header
7
8
10
9
JTAG_RST_B
to CPLD
1.8V
41