Page 1 QorIQ LS1012A Reference Manual Document Number: LS1012ARM Rev. 1, 01/2018...
Page 2 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 3 Integrated interchip sound (I2S) / synchronous audio interface (SAI)............185 1.4.12 Enhanced secure digital host controller and SDIO..................186 1.4.13 Integrated security engine (SEC)........................186 1.4.14 Inter-integrated circuit (I2C) controller......................187 1.4.15 Quad serial peripheral interface (QuadSPI)....................187 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 4 TA_TMP_DETECT_B and GPIO2 signal multiplexing................218 Output Signal States During Reset..........................219 Chapter 4 Reset, Clocking, and Initialization Reset, clocking, and initialization overview......................... 221 External Signal Descriptions............................221 4.2.1 System control signals........................... 222 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 5 Offset............................229 4.3.5.2 Function............................. 229 4.3.5.3 Diagram............................229 4.3.5.4 Fields............................229 Functional description..............................230 4.4.1 Power-on reset sequence..........................230 4.4.2 Core Soft Reset.............................. 233 4.4.3 Reset state timing............................233 4.4.4 Power-on reset configuration......................... 234 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 6 Internal interrupt sources.............................. 257 Chapter 6 Arm Modules Introduction...................................261 Arm® Cortex®-A53 core............................. 261 Arm generic interrupt controller (GIC-400)......................... 262 On-Chip RAM memory controller (OCRAM)......................263 Chapter 7 CSU, OCRAM, and MSCM QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 7 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)..........296 7.3.2.12 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)..........297 Chapter 8 System Counter Overview..................................299 Secure system counter register descriptions......................... 299 8.2.1 Secure_System_counter Memory map......................299 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 8 Non_secure_system_counter Memory map....................304 8.3.2 LSB of Counter Count Value (CNCTV_RO1)....................304 8.3.2.1 Offset............................304 8.3.2.2 Function............................. 304 8.3.2.3 Diagram............................305 8.3.2.4 Fields............................305 8.3.3 MSB of counter count value register (CNCTV2_RO2).................305 8.3.3.1 Offset............................305 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 9 Secure Access Register (Secure_Access_Register)..................316 9.2.4.1 Offset............................316 9.2.4.2 Function............................. 316 9.2.4.3 Diagram............................316 9.2.4.4 Fields............................317 9.2.5 Status Register (Status_Register)........................317 9.2.5.1 Offset............................317 9.2.5.2 Function............................. 317 9.2.5.3 Diagram............................318 9.2.5.4 Fields............................318 9.2.6 Imprecise Error Register (Imprecise_Error_Register)................... 319 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 10 Write Qos Override Register (Write_Qos_Override_Register_S0 - Write_Qos_Override_Register_S4)..325 9.2.10.1 Offset............................325 9.2.10.2 Function............................. 326 9.2.10.3 Diagram............................326 9.2.10.4 Fields............................326 9.2.11 Qos Control Register (Qos_Control_Register_S0 - Qos_Control_Register_S4).......... 327 9.2.11.1 Offset............................327 9.2.11.2 Function............................. 327 9.2.11.3 Diagram............................327 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 11 9.3.1 About the functions............................336 9.3.2 Snoop connectivity and control........................336 9.3.2.1 Removing a master from the coherent domain................337 9.3.3 Speculative fetch............................337 9.3.4 Security................................338 9.3.4.1 Internal programmers view......................338 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 12 Offset............................352 10.3.2.2 Function............................. 352 10.3.2.3 Diagram............................352 10.3.2.4 Fields............................352 10.3.3 Action register (action)..........................353 10.3.3.1 Offset............................353 10.3.3.2 Function............................. 353 10.3.3.3 Diagram............................353 10.3.3.4 Fields............................354 10.3.4 Lockdown Range Register (lockdown_range)....................354 10.3.4.1 Offset............................354 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 13 Offset............................360 10.3.8.2 Function............................. 360 10.3.8.3 Diagram............................360 10.3.8.4 Fields............................361 10.3.9 Fail Address High Register (fail_address_high).................... 361 10.3.9.1 Offset............................361 10.3.9.2 Function............................. 361 10.3.9.3 Diagram............................361 10.3.9.4 Fields............................361 10.3.10 Fail Control Register (fail_control)........................362 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 14 Offset............................367 10.3.14.2 Diagram............................367 10.3.14.3 Fields............................368 10.3.15 Region Setup High 0 Register (region_setup_high_0).................. 368 10.3.15.1 Offset............................368 10.3.15.2 Function............................. 368 10.3.15.3 Diagram............................368 10.3.15.4 Fields............................369 10.3.16 Region Attributes 0 Register (region_attributes_0)..................369 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 15 Diagram............................376 10.3.20.3 Fields............................376 10.3.21 Region Setup High 2 Register (region_setup_high_2).................. 377 10.3.21.1 Offset............................377 10.3.21.2 Function............................. 377 10.3.21.3 Diagram............................377 10.3.21.4 Fields............................378 10.3.22 Region Attributes 2 Register (region_attributes_2)..................378 10.3.22.1 Offset............................378 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 16 Fields............................387 10.3.27 Region Setup High 4 Register (region_setup_high_4).................. 388 10.3.27.1 Offset............................388 10.3.27.2 Function............................. 388 10.3.27.3 Diagram............................388 10.3.27.4 Fields............................389 10.3.28 Region Attributes 4 Register (region_attributes_4)..................389 10.3.28.1 Offset............................389 10.3.28.2 Function............................. 389 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 17 10.3.33 Region Setup High 6 Register (region_setup_high_6).................. 399 10.3.33.1 Offset............................399 10.3.33.2 Function............................. 399 10.3.33.3 Diagram............................399 10.3.33.4 Fields............................400 10.3.34 Region Attributes 6 Register (region_attributes_6)..................400 10.3.34.1 Offset............................400 10.3.34.2 Function............................. 400 10.3.34.3 Diagram............................402 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 18 10.3.39 Region Setup High 8 Register (region_setup_high_8).................. 410 10.3.39.1 Offset............................410 10.3.39.2 Function............................. 410 10.3.39.3 Diagram............................410 10.3.39.4 Fields............................411 10.3.40 Region Attributes 8 Register (region_attributes_8)..................411 10.3.40.1 Offset............................411 10.3.40.2 Function............................. 411 10.3.40.3 Diagram............................413 10.3.40.4 Fields............................413 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 19 Function............................. 421 10.3.45.3 Diagram............................421 10.3.45.4 Fields............................422 10.3.46 Region Attributes 10 Register (region_attributes_10)................... 422 10.3.46.1 Offset............................422 10.3.46.2 Function............................. 422 10.3.46.3 Diagram............................424 10.3.46.4 Fields............................424 10.3.47 Region Setup Low 11 Register (region_setup_low_11)................425 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 20 Diagram............................432 10.3.51.4 Fields............................433 10.3.52 Region Attributes 12 Register (region_attributes_12)................... 433 10.3.52.1 Offset............................433 10.3.52.2 Function............................. 433 10.3.52.3 Diagram............................435 10.3.52.4 Fields............................435 10.3.53 Region Setup Low 13 Register (region_setup_low_13)................436 10.3.53.1 Offset............................436 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 21 Fields............................444 10.3.58 Region Attributes 14 Register (region_attributes_14)................... 444 10.3.58.1 Offset............................444 10.3.58.2 Function............................. 444 10.3.58.3 Diagram............................446 10.3.58.4 Fields............................446 10.3.59 Region Setup Low 15 Register (region_setup_low_15)................447 10.3.59.1 Offset............................447 10.3.59.2 Diagram............................447 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 22 10.3.63.3 Diagram............................454 10.3.63.4 Fields............................455 10.3.64 Integration Test Output Register (itop)......................455 10.3.64.1 Offset............................455 10.3.64.2 Function............................. 455 10.3.64.3 Diagram............................456 10.3.64.4 Fields............................456 10.4 Functional description..............................456 10.4.1 Functional operation............................457 10.4.1.1 Regions............................457 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 23 USB3 parameter 2 control register (USB3PRM2CR)................... 475 11.2.3.1 Offset............................475 11.2.3.2 Function............................. 475 11.2.3.3 Diagram............................475 11.2.3.4 Fields............................475 11.2.4 USB3 parameter 3 control register (USB3PRM3CR)................... 476 11.2.4.1 Offset............................476 11.2.4.2 Function............................. 476 11.2.4.3 Diagram............................476 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 24 11.2.8.3 Diagram............................481 11.2.8.4 Fields............................481 11.2.9 WR_QoS1 register (WR_QoS1)........................482 11.2.9.1 Offset............................482 11.2.9.2 Function............................. 482 11.2.9.3 Diagram............................482 11.2.9.4 Fields............................483 11.2.10 WR QoS2 register (WR_QoS2)........................483 11.2.10.1 Offset............................483 11.2.10.2 Function............................. 484 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 25 Fields............................489 11.2.15 Core reset vector base address register 0 (RVBAR0_0)................490 11.2.15.1 Offset............................490 11.2.15.2 Function............................. 490 11.2.15.3 Diagram............................490 11.2.15.4 Fields............................491 11.2.16 Core reset vector base address register 0 (RVBAR0_1)................491 11.2.16.1 Offset............................491 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 26 11.2.20.2 Function............................. 496 11.2.20.3 Diagram............................496 11.2.20.4 Fields............................497 11.2.21 Cluster PM control register (CLUSTERPMCR)................... 497 11.2.21.1 Offset............................497 11.2.21.2 Function............................. 498 11.2.21.3 Diagram............................498 11.2.21.4 Fields............................498 11.2.22 Pinmux control register (PMUXCR0)......................498 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 27 11.2.26 PFE interrupt enable control register (PFEINTENCR1)................504 11.2.26.1 Offset............................504 11.2.26.2 Function............................. 504 11.2.26.3 Diagram............................504 11.2.26.4 Fields............................504 11.2.27 PFE PCS status register 2 (PFEPCSSR2)...................... 505 11.2.27.1 Offset............................505 11.2.27.2 Function............................. 505 11.2.27.3 Diagram............................505 11.2.27.4 Fields............................505 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 28 Fields............................510 11.2.32 PFEB sideband control register (PFEBSBCR)....................511 11.2.32.1 Offset............................511 11.2.32.2 Function............................. 511 11.2.32.3 Diagram............................511 11.2.32.4 Fields............................512 11.2.33 MDIO select control register (MDIOSELCR)....................512 11.2.33.1 Offset............................513 11.2.33.2 Function............................. 513 11.2.33.3 Diagram............................513 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 29 11.2.38 Shared message signaled interrupt index register (PEX1MSIIR)..............518 11.2.38.1 Offset............................518 11.2.38.2 Function............................. 518 11.2.38.3 Diagram............................519 11.2.38.4 Fields............................519 11.2.39 Shared message signaled interrupt register (PEX1MSIR)................519 11.2.39.1 Offset............................519 11.2.39.2 Function............................. 519 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 30 Offset............................525 12.3.4.2 Function............................. 526 12.3.4.3 Diagram............................526 12.3.4.4 Fields............................526 12.3.5 Device Disable Register 1 (DEVDISR1).......................527 12.3.5.1 Offset............................527 12.3.5.2 Function............................. 528 12.3.5.3 Diagram............................528 12.3.5.4 Fields............................528 12.3.6 Device Disable Register 2 (DEVDISR2).......................529 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 31 12.3.10 System Version Register (SVR)........................536 12.3.10.1 Offset............................536 12.3.10.2 Function............................. 536 12.3.10.3 Diagram............................536 12.3.10.4 Fields............................536 12.3.11 Reset Control Register (RSTCR)........................537 12.3.11.1 Offset............................537 12.3.11.2 Function............................. 537 12.3.11.3 Diagram............................537 12.3.11.4 Fields............................537 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 32 12.3.16 Reset Control Word Status Register n (RCWSR0 - RCWSR15)..............545 12.3.16.1 Offset............................545 12.3.16.2 Function............................. 545 12.3.16.3 Diagram............................545 12.3.16.4 Fields............................546 12.3.17 Scratch Read / Write Register n (SCRATCHRW1 - SCRATCHRW4)............546 12.3.17.1 Offset............................546 12.3.17.2 Function............................. 546 12.3.17.3 Diagram............................547 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 33 12.3.21.4 Fields............................552 12.3.22 Core Cluster n Topology Register (TP_CLUSTER1)................... 552 12.3.22.1 Offset............................552 12.3.22.2 Function............................. 553 12.3.22.3 Diagram............................553 12.3.22.4 Fields............................553 Chapter 13 Run Control and Power Management (RCPM) 13.1 Introduction...................................555 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 34 Power Management Control and Status Register (POWMGTCSR)............. 564 13.3.3.1 Offset............................564 13.3.3.2 Function............................. 564 13.3.3.3 Diagram............................564 13.3.3.4 Fields............................565 13.3.4 IP Powerdown Exception Control Register (IPPDEXPCR)................566 13.3.4.1 Offset............................566 13.3.4.2 Function............................. 566 13.3.4.3 Diagram............................566 13.3.4.4 Fields............................567 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 35 Modes of operation............................577 15.3 DUART external signal descriptions..........................577 15.4 DUART register descriptions............................578 15.4.1 DUART Memory map........................... 578 15.4.2 UART divisor least significant byte register (UDLB1 - UDLB2)..............579 15.4.2.1 Offset............................579 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 36 15.4.6.4 Fields............................584 15.4.7 UART alternate function register (UAFR1 - UAFR2).................. 585 15.4.7.1 Offset............................585 15.4.7.2 Function............................. 585 15.4.7.3 Diagram............................585 15.4.7.4 Fields............................586 15.4.8 UART FIFO control register (UFCR1 - UFCR2)..................586 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 37 15.4.12 UART scratch register (USCR1 - USCR2)....................594 15.4.12.1 Offset............................594 15.4.12.2 Function............................. 594 15.4.12.3 Diagram............................594 15.4.12.4 Fields............................595 15.4.13 UART DMA status register (UDSR1 - UDSR2)................... 595 15.4.13.1 Offset............................595 15.4.13.2 Function............................. 595 15.4.13.3 Diagram............................596 15.4.13.4 Fields............................597 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 38 DMAMUX......................603 16.1.2.1.1 eDMA and DMAMUX channel assignment............604 16.1.2.1.2 DMAMUX settings.....................604 16.1.2.1.3 DMAMUX request sources................604 16.2 Introduction...................................607 16.2.1 Overview................................ 607 16.2.2 Features................................608 16.2.3 Modes of operation............................608 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 39 Features................................619 17.3 Modes of operation............................... 621 17.4 Memory map/register definition........................... 621 17.4.1 TCD memory..............................621 17.4.2 TCD initialization............................621 17.4.3 TCD structure..............................622 17.4.4 Reserved memory and bit fields........................622 17.4.5 Endianness..............................622 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 40 Function......................654 17.4.6.5.3 Diagram.......................654 17.4.6.5.4 Fields........................654 17.4.6.6 Set Enable Request Register (SERQ)..................656 17.4.6.6.1 Offset........................656 17.4.6.6.2 Function......................657 17.4.6.6.3 Diagram.......................657 17.4.6.6.4 Fields........................657 17.4.6.7 Clear Enable Request Register (CERQ)..................658 17.4.6.7.1 Offset........................658 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 41 17.4.6.11.2 Function......................662 17.4.6.11.3 Diagram.......................663 17.4.6.11.4 Fields........................663 17.4.6.12 Set START Bit Register (SSRT)....................663 17.4.6.12.1 Offset........................663 17.4.6.12.2 Function......................663 17.4.6.12.3 Diagram.......................664 17.4.6.12.4 Fields........................664 17.4.6.13 Clear DONE Status Bit Register (CDNE)................. 664 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 42 17.4.6.17.1 Offset........................677 17.4.6.17.2 Function......................678 17.4.6.17.3 Diagram.......................678 17.4.6.17.4 Register reset values................... 678 17.4.6.17.5 Fields........................679 17.4.6.18 Channel n Master ID Register (DCHMID0 - DCHMID31)............680 17.4.6.18.1 Offset........................680 17.4.6.18.2 Function......................680 17.4.6.18.3 Diagram.......................680 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 43 (TCD0_NBYTES_MLOFFNO - TCD31_NBYTES_MLOFFNO).......... 685 17.4.6.23.1 Offset........................685 17.4.6.23.2 Function......................685 17.4.6.23.3 Diagram.......................686 17.4.6.23.4 Fields........................686 17.4.6.24 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0_NBY TES_MLOFFYES - TCD31_NBYTES_MLOFFYES).............687 17.4.6.24.1 Offset........................687 17.4.6.24.2 Function......................687 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 44 17.4.6.28.4 Fields........................692 17.4.6.29 TCD Signed Destination Address Offset (TCD0_DOFF - TCD31_DOFF)......693 17.4.6.29.1 Offset........................693 17.4.6.29.2 Diagram.......................693 17.4.6.29.3 Fields........................693 17.4.6.30 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA - TCD31_DLASTSGA)....................... 693 17.4.6.30.1 Offset........................693 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 45 705 17.6.2 Programming errors............................707 17.6.3 Arbitration mode considerations........................708 17.6.3.1 Fixed group arbitration, Fixed channel arbitration..............708 17.6.3.2 Fixed group arbitration, Round-robin channel arbitration............709 17.6.4 Performing DMA transfers..........................709 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 46 18.1.3 LS1012A eSDHC module special consideration................... 724 18.2 Overview..................................725 18.2.1 eSDHC features summary..........................727 18.2.2 Modes and operations............................ 728 18.2.2.1 Data transfer modes........................728 18.3 External signals................................729 18.3.1 External signals overview..........................729 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 47 Function............................. 736 18.4.5.3 Diagram............................737 18.4.5.4 Fields............................737 18.4.6 Command response 0 register (CMDRSP0)....................740 18.4.6.1 Offset............................740 18.4.6.2 Function............................. 740 18.4.6.3 Diagram............................740 18.4.6.4 Fields............................740 18.4.7 Command response 1 register (CMDRSP1)....................741 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 48 Fields............................745 18.4.11 Present state register (PRSSTAT)........................746 18.4.11.1 Offset............................746 18.4.11.2 Function............................. 746 18.4.11.3 Diagram............................746 18.4.11.4 Fields............................746 18.4.12 Protocol control register (PROCTL)......................750 18.4.12.1 Offset............................750 18.4.12.2 Function............................. 750 18.4.12.3 Diagram............................751 18.4.12.4 Fields............................751 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 49 18.4.17.2 Function............................. 768 18.4.17.3 Diagram............................768 18.4.17.4 Fields............................768 18.4.18 Auto CMD Error Status Register / System Control 2 Register (AUTOCERR_SYSCTL2)......770 18.4.18.1 Offset............................770 18.4.18.2 Function............................. 770 18.4.18.3 Diagram............................771 18.4.18.4 Fields............................772 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 50 Fields............................781 18.4.23 ADMA system address register (ADSADDR)....................781 18.4.23.1 Offset............................782 18.4.23.2 Function............................. 782 18.4.23.3 Diagram............................782 18.4.23.4 Fields............................782 18.4.24 Host controller version register (HOSTVER)....................782 18.4.24.1 Offset............................783 18.4.24.2 Function............................. 783 18.4.24.3 Diagram............................783 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 51 18.4.28.4 Fields............................788 18.4.29 Tuning block status register (TBSTAT)......................789 18.4.29.1 Offset............................789 18.4.29.2 Function............................. 790 18.4.29.3 Diagram............................790 18.4.29.4 Fields............................790 18.4.30 Tuning block pointer register (TBPTR)......................790 18.4.30.1 Offset............................790 18.4.30.2 Function............................. 791 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 52 Dividing large data transfer................803 18.5.1.1.5 Byte order (endianness) of buffer data port register........... 804 18.5.1.2 DMA system interface....................... 805 18.5.1.2.1 DMA burst length....................806 18.5.1.2.2 System master interface..................806 18.5.1.3 Single DMA (SDMA)........................ 807 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 53 Command send and response receive basic operation................... 823 18.6.2 Card identification mode..........................824 18.6.2.1 Card detect..........................824 18.6.2.2 Reset............................825 18.6.2.3 Voltage validation........................826 18.6.2.4 Card registry..........................828 18.6.3 Card access..............................829 18.6.3.1 Block write..........................829 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 54 Query, enable and disable eMMC high speed mode..............842 18.6.4.4 Set eMMC bus width......................... 843 18.6.5 ADMA operation............................843 18.6.5.1 ADMA1 operation........................843 18.6.5.2 ADMA2 operation........................843 18.7 Interfacing Card................................844 18.8 Commands for /SD/SDIO and eMMC device......................845 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 55 Memory map and register definition..........................862 19.4.1 Memory map..............................862 19.4.2 Register descriptions............................863 19.4.3 Status And Control (FTMx_SC)........................866 19.4.4 Counter (FTMx_CNT)........................... 868 19.4.5 Modulo (FTMx_MOD)..........................868 19.4.6 Channel (n) Status And Control (FTMx_CnSC)....................869 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 56 19.4.27 FTM PWM Load (FTMx_PWMLOAD)....................... 907 19.5 Functional description..............................908 19.5.1 Clock source..............................909 19.5.1.1 Counter clock source........................909 19.5.2 Prescaler................................. 910 19.5.3 Counter................................910 19.5.3.1 Up counting..........................910 19.5.3.2 Up-down counting........................913 19.5.3.3 Free running counter........................914 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 57 19.5.11.8 INVCTRL register synchronization...................944 19.5.11.9 SWOCTRL register synchronization..................945 19.5.11.10 FTM counter synchronization....................947 19.5.12 Inverting................................. 950 19.5.13 Software output control..........................951 19.5.14 Deadtime insertion............................953 19.5.14.1 Deadtime insertion corner cases....................954 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 58 19.5.27 Global time base (GTB)..........................981 19.5.27.1 Enabling the global time base (GTB)..................982 19.6 Reset overview................................982 19.7 FTM Interrupts................................984 19.7.1 Timer Overflow Interrupt..........................984 19.7.2 Channel (n) Interrupt............................984 19.7.3 Fault Interrupt..............................984 19.8 Initialization Procedure..............................984 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 59 Offset............................992 20.5.4.2 Function............................. 992 20.5.4.3 Diagram............................992 20.5.4.4 Fields............................992 20.5.5 GPIO interrupt event register (GPIER)......................993 20.5.5.1 Offset............................993 20.5.5.2 Function............................. 993 20.5.5.3 Diagram............................993 20.5.5.4 Fields............................994 20.5.6 GPIO interrupt mask register (GPIMR)......................994 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 60 Definition: I2C conditions..........................1002 21.4 External signal descriptions............................1003 21.4.1 Signal overview..............................1003 21.4.2 Detailed external signal descriptions......................1003 21.5 Memory map and register definition..........................1003 21.5.1 Register accessibility............................1004 21.5.2 Register figure conventions........................... 1004 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 61 Clock stretching......................... 1017 21.6.4.3 Handshaking..........................1017 21.6.4.4 Clock rate and IBFD settings..................... 1017 21.6.4.4.1 Timing definitions....................1018 21.6.4.4.2 Divider and hold values..................1018 21.6.5 Interrupts................................ 1023 21.6.5.1 Interrupt vector...........................1024 21.6.5.2 Interrupt description........................1024 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 62 22.1.2 I2Sx_TCR2[MSEL] and I2Sx_RCR2[MSEL] mapping................1042 22.1.3 LS1012A SAI/I2S module special consideration..................1042 22.2 Introduction...................................1042 22.2.1 Features................................1042 22.2.2 Block diagram..............................1043 22.2.3 Modes of operation............................1043 22.2.3.1 Run mode........................... 1043 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 63 22.5.1 SAI clocking..............................1069 22.5.1.1 Audio master clock........................1069 22.5.1.2 Bit clock............................. 1069 22.5.1.3 Bus clock............................1070 22.5.2 SAI resets............................... 1070 22.5.2.1 Software reset..........................1071 22.5.2.2 FIFO reset..........................1071 22.5.3 Synchronous modes............................1071 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 64 MMDC Address Space..........................1083 23.3.3.1 Address decoding ........................1083 23.3.4 Power Saving and Clock Frequency Change modes..................1085 23.3.4.1 Power saving general......................... 1085 23.3.4.2 Self refresh and Frequency change entry/exit................1086 23.3.5 Reset ................................1088 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 65 23.8.2.1.2 ZQ automatic Pull-down calibration..............1102 23.8.2.2 ZQ software calibration process....................1102 23.8.2.2.1 ZQ software Pull-up calibration................1103 23.8.2.2.2 ZQ software Pull-down calibration..............1103 23.8.2.2.3 ZQ calibration commands ..................1103 23.8.3 Read DQS Gating Calibration........................1104 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 66 ZQ Fine Tuning..............................1121 23.8.10 Duty cycle adjustment............................1122 23.9 MMDC Memory Map/Register Definition........................1122 23.9.1 MMDC register descriptions..........................1122 23.9.1.1 MMDC Memory map........................ 1122 23.9.1.2 MMDC Core Control Register (MDCTL)................. 1124 23.9.1.2.1 Offset........................1124 23.9.1.2.2 Diagram.......................1124 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 67 MMDC Core Timing Configuration Register 2 (MDCFG2).............1135 23.9.1.7.1 Offset........................1135 23.9.1.7.2 Diagram.......................1135 23.9.1.7.3 Fields........................1135 23.9.1.8 MMDC Core Miscellaneous Register (MDMISC)..............1136 23.9.1.8.1 Offset........................1136 23.9.1.8.2 Diagram.......................1137 23.9.1.8.3 Fields........................1137 23.9.1.9 MMDC Core Special Command Register (MDSCR)..............1138 23.9.1.9.1 Offset........................1139 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 68 Diagram.......................1147 23.9.1.13.4 Fields........................1147 23.9.1.14 MMDC Core Power Saving Control and Status Register (MAPSR).........1149 23.9.1.14.1 Offset........................1149 23.9.1.14.2 Function......................1149 23.9.1.14.3 Diagram.......................1149 23.9.1.14.4 Fields........................1149 23.9.1.15 MMDC Core Exclusive ID Monitor Register0 (MAEXIDR0)..........1151 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 69 MMDC Core Debug and Profiling Status Register 1 (MADPSR1).......... 1156 23.9.1.20.1 Offset........................1156 23.9.1.20.2 Function......................1156 23.9.1.20.3 Diagram.......................1156 23.9.1.20.4 Fields........................1157 23.9.1.21 MMDC Core Debug and Profiling Status Register 2 (MADPSR2).......... 1157 23.9.1.21.1 Offset........................1157 23.9.1.21.2 Function......................1157 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 70 Fields........................1162 23.9.1.26 MMDC Core Step By Step Address Attributes Register (MASBS1)........1162 23.9.1.26.1 Offset........................1162 23.9.1.26.2 Diagram.......................1162 23.9.1.26.3 Fields........................1162 23.9.1.27 MMDC Core General Purpose Register (MAGENP)..............1163 23.9.1.27.1 Offset........................1163 23.9.1.27.2 Function......................1164 23.9.1.27.3 Diagram.......................1164 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 71 Diagram.......................1174 23.9.1.32.4 Fields........................1175 23.9.1.33 MMDC PHY ODT control register (MPODTCTRL)..............1176 23.9.1.33.1 Offset........................1176 23.9.1.33.2 Diagram.......................1176 23.9.1.33.3 Fields........................1176 23.9.1.34 MMDC PHY Read DQ Byte0 Delay Register (MPRDDQBY0DL)......... 1177 23.9.1.34.1 Offset........................1177 23.9.1.34.2 Function......................1178 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 72 MMDC PHY Read DQS Gating delay-line Status Register (MPDGDLST0)......1191 23.9.1.39.1 Offset........................1192 23.9.1.39.2 Function......................1192 23.9.1.39.3 Diagram.......................1192 23.9.1.39.4 Fields........................1192 23.9.1.40 MMDC PHY Read delay-lines Configuration Register (MPRDDLCTL).........1193 23.9.1.40.1 Offset........................1193 23.9.1.40.2 Function......................1193 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 73 23.9.1.45 MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL)....1200 23.9.1.45.1 Offset........................1200 23.9.1.45.2 Diagram.......................1201 23.9.1.45.3 Fields........................1201 23.9.1.46 MMDC PHY Write Delay HW Calibration Control Register (MPWRDLHWCTL)....1202 23.9.1.46.1 Offset........................1202 23.9.1.46.2 Diagram.......................1202 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 74 MMDC PHY Pre-defined Compare Register 1 (MPPDCMPR1)..........1209 23.9.1.52.1 Offset........................1209 23.9.1.52.2 Function......................1209 23.9.1.52.3 Diagram.......................1210 23.9.1.52.4 Fields........................1210 23.9.1.53 MMDC PHY Pre-defined Compare and CA delay-line Configuration Register (MPPD CMPR2)............................. 1210 23.9.1.53.1 Offset........................1211 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 75 MMDC PHY SW Dummy Read Data Register 4 (MPSWDRDR4)......... 1218 23.9.1.59.1 Offset........................1218 23.9.1.59.2 Diagram.......................1218 23.9.1.59.3 Fields........................1218 23.9.1.60 MMDC PHY SW Dummy Read Data Register 5 (MPSWDRDR5)......... 1219 23.9.1.60.1 Offset........................1219 23.9.1.60.2 Diagram.......................1219 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 76 Device configuration using reset configuration word (RCW)............... 1228 24.4.2 Device initialization by PBL..........................1229 24.4.2.1 CCSR registers blocked from PBL during secure boot............. 1229 24.4.3 Required format of data structure used by PBL.....................1230 24.4.4 RCW loading by PBL............................ 1232 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 77 25.3 External Signal Descriptions............................1243 25.4 Memory map/register overview............................1244 25.4.1 PCI Express configuration registers.......................1244 25.4.2 PEX register descriptions..........................1245 25.4.2.1 PCI_Express_Configuration_Registers Memory map...............1245 25.4.2.2 PCI Express Vendor ID Register (Vendor_ID_Register)............1249 25.4.2.2.1 Offset........................1249 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 78 Function......................1254 25.4.2.6.3 Diagram.......................1255 25.4.2.6.4 Fields........................1255 25.4.2.7 PCI Express Class Code Register (Class_Code_Register)............1255 25.4.2.7.1 Offset........................1255 25.4.2.7.2 Function......................1255 25.4.2.7.3 Diagram.......................1255 25.4.2.7.4 Fields........................1256 25.4.2.8 PCI Express Cache Line Size Register (Cache_Line_Size_Register)........1256 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 79 PCI Express Base Address Register 1 (BAR1)................1260 25.4.2.12.1 Offset........................1260 25.4.2.12.2 Function......................1260 25.4.2.12.3 Diagram.......................1260 25.4.2.12.4 Fields........................1261 25.4.2.13 PCI Express Base Address Register 2 (BAR2)................1261 25.4.2.13.1 Offset........................1261 25.4.2.13.2 Function......................1261 25.4.2.13.3 Diagram.......................1261 25.4.2.13.4 Fields........................1262 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 80 PCI Express I/O Base Register (IO_Base_Register)..............1265 25.4.2.18.1 Offset........................1265 25.4.2.18.2 Function......................1266 25.4.2.18.3 Diagram.......................1266 25.4.2.18.4 Fields........................1266 25.4.2.19 PCI Express I/O Limit Register (IO_Limit_Register)............... 1266 25.4.2.19.1 Offset........................1267 25.4.2.19.2 Function......................1267 25.4.2.19.3 Diagram.......................1267 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 81 25.4.2.24 PCI Express Base Address Register 5 (BAR5)................1272 25.4.2.24.1 Offset........................1272 25.4.2.24.2 Function......................1272 25.4.2.24.3 Diagram.......................1272 25.4.2.24.4 Fields........................1272 25.4.2.25 PCI Express Prefetchable Memory Base Register (Prefetchable_Memory_Base_Register)..1273 25.4.2.25.1 Offset........................1273 25.4.2.25.2 Function......................1273 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 82 PCI Express Subsystem Vendor ID Register (Subsystem_Vendor_ID_Register)....1276 25.4.2.29.1 Offset........................1277 25.4.2.29.2 Function......................1277 25.4.2.29.3 Diagram.......................1277 25.4.2.29.4 Fields........................1277 25.4.2.30 PCI Express Subsystem ID Register (Subsystem_ID_Register)..........1277 25.4.2.30.1 Offset........................1277 25.4.2.30.2 Function......................1278 25.4.2.30.3 Diagram.......................1278 25.4.2.30.4 Fields........................1278 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 83 Fields........................1281 25.4.2.35 PCI Express Expansion ROM Base Address Register (RC-Mode) (Expansion_ROM_BAR_ Type1)............................1282 25.4.2.35.1 Offset........................1282 25.4.2.35.2 Function......................1282 25.4.2.35.3 Diagram.......................1282 25.4.2.35.4 Fields........................1282 25.4.2.36 PCI Express Interrupt Line Register (Interrupt_Line_Register)..........1283 25.4.2.36.1 Offset........................1283 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 84 PCI Express Maximum Latency Register (Maximum_Latency_Register)....... 1286 25.4.2.40.1 Offset........................1286 25.4.2.40.2 Function......................1287 25.4.2.40.3 Diagram.......................1287 25.4.2.40.4 Fields........................1287 25.4.2.41 PCI Express Power Management Capability ID Register (Power_Management_Capability_ ID_Register)..........................1287 25.4.2.41.1 Offset........................1287 25.4.2.41.2 Diagram.......................1287 25.4.2.41.3 Fields........................1287 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 85 PCI Express MSI Message Control Register (MSI_Message_Control_Register).....1292 25.4.2.46.1 Offset........................1292 25.4.2.46.2 Function......................1292 25.4.2.46.3 Diagram.......................1292 25.4.2.46.4 Fields........................1292 25.4.2.47 PCI Express MSI Message Address Register (MSI_Message_Address_Register)....1293 25.4.2.47.1 Offset........................1293 25.4.2.47.2 Function......................1293 25.4.2.47.3 Diagram.......................1293 25.4.2.47.4 Fields........................1293 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 86 PCI Express Device Capabilities Register (Device_Capabilities_Register)......1297 25.4.2.52.1 Offset........................1297 25.4.2.52.2 Diagram.......................1298 25.4.2.52.3 Fields........................1298 25.4.2.53 PCI Express Device Control Register (Device_Control_Register)........... 1299 25.4.2.53.1 Offset........................1299 25.4.2.53.2 Diagram.......................1299 25.4.2.53.3 Fields........................1299 25.4.2.54 PCI Express Device Status Register (Device_Status_Register)..........1300 25.4.2.54.1 Offset........................1300 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 87 PCI Express Slot Control Register (Slot_Control_Register)............. 1307 25.4.2.59.1 Offset........................1307 25.4.2.59.2 Function......................1307 25.4.2.59.3 Diagram.......................1307 25.4.2.59.4 Fields........................1308 25.4.2.60 PCI Express Slot Status Register (Slot_Status_Register)............1308 25.4.2.60.1 Offset........................1309 25.4.2.60.2 Function......................1309 25.4.2.60.3 Diagram.......................1309 25.4.2.60.4 Fields........................1309 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 88 25.4.2.65.2 Diagram.......................1314 25.4.2.65.3 Fields........................1314 25.4.2.66 PCI Express Link Capabilities 2 Register (Link_Capabilities_2_Register)......1315 25.4.2.66.1 Offset........................1315 25.4.2.66.2 Function......................1315 25.4.2.66.3 Diagram.......................1315 25.4.2.66.4 Fields........................1316 25.4.2.67 PCI Express Link Control 2 Register (Link_Control_2_Register)..........1316 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 89: Table Of Contents
Fields........................1321 25.4.2.72 PCI Express Uncorrectable Error Severity Register (Uncorrectable_Error_Severity_Registe r)..............................1322 25.4.2.72.1 Offset........................1322 25.4.2.72.2 Diagram.......................1322 25.4.2.72.3 Fields........................1323 25.4.2.73 PCI Express Correctable Error Status Register (Correctable_Error_Status_Register)....1324 25.4.2.73.1 Offset........................1324 25.4.2.73.2 Diagram.......................1324 25.4.2.73.3 Fields........................1324 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 90 PCI Express Header Log Register 3 (Header_Log_Register_DWORD3)........ 1329 25.4.2.78.1 Offset........................1329 25.4.2.78.2 Function......................1330 25.4.2.78.3 Diagram.......................1330 25.4.2.78.4 Fields........................1330 25.4.2.79 PCI Express Header Log Register 4 (Header_Log_Register_DWORD4)........ 1330 25.4.2.79.1 Offset........................1330 25.4.2.79.2 Function......................1331 25.4.2.79.3 Diagram.......................1331 25.4.2.79.4 Fields........................1331 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 91 Secondary PCI Express Extended Capability Header (SPCIE_CAP_HEADER_REG)... 1335 25.4.2.84.1 Offset........................1335 25.4.2.84.2 Diagram.......................1335 25.4.2.84.3 Fields........................1336 25.4.2.85 Link Control 3 Register (LINK_CONTROL3_REG)............... 1336 25.4.2.85.1 Offset........................1336 25.4.2.85.2 Diagram.......................1336 25.4.2.85.3 Fields........................1337 25.4.2.86 Lane Error Status Register (LANE_ERR_STATUS_REG)............1337 25.4.2.86.1 Offset........................1337 25.4.2.86.2 Diagram.......................1337 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 92 Coherency Control Register 1 (COHERENCY_CONTROL_1_OFF)........1345 25.4.2.91.1 Offset........................1345 25.4.2.91.2 Diagram.......................1345 25.4.2.91.3 Fields........................1345 25.4.2.92 Coherency Control Register 2 (COHERENCY_CONTROL_2_OFF)........1346 25.4.2.92.1 Offset........................1346 25.4.2.92.2 Diagram.......................1346 25.4.2.92.3 Fields........................1346 25.4.2.93 Coherency Control Register 3 (COHERENCY_CONTROL_3_OFF)........1347 25.4.2.93.1 Offset........................1347 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 93 Region Control 2 Register (IATU_REGION_CTRL_2_OFF_OUTBOUND_0)... 1354 25.4.2.98.1 Offset........................1354 25.4.2.98.2 Diagram.......................1354 25.4.2.98.3 Fields........................1355 25.4.2.99 iATU Lower Base Address Register (IATU_LWR_BASE_ADDR_OFF_INBOUND_0)..1356 25.4.2.99.1 Offset........................1356 25.4.2.99.2 Diagram.......................1356 25.4.2.99.3 Fields........................1356 25.4.2.100 iATU Lower Base Address Register (IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0).. 1356 25.4.2.100.1 Offset........................1356 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 94 25.4.2.105 iATU Region#N Lower Offset Address Register (IATU_LWR_TARGET_ADDR_OFF_ INBOUND_0)..........................1361 25.4.2.105.1 Offset........................1361 25.4.2.105.2 Diagram.......................1361 25.4.2.105.3 Fields........................1362 25.4.2.106 iATU Outbound Region#N Lower Offset Address Register (IATU_LWR_TARGET_ ADDR_OFF_OUTBOUND_0)....................1362 25.4.2.106.1 Offset........................1362 25.4.2.106.2 Diagram.......................1363 25.4.2.106.3 Fields........................1363 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 95 25.4.2.111 Base Address Register 2 Mask (BAR2_MASK)............... 1367 25.4.2.111.1 Offset........................1367 25.4.2.111.2 Function......................1367 25.4.2.111.3 Diagram.......................1368 25.4.2.111.4 Fields........................1368 25.4.2.112 Base Address Register 3 Mask (BAR3_MASK)............... 1368 25.4.2.112.1 Offset........................1368 25.4.2.112.2 Function......................1368 25.4.2.112.3 Diagram.......................1369 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 96 25.4.2.116.4 Fields........................1374 25.5 PEX_LUT memory map/registers overview........................ 1374 25.5.1 PEX_LUT register descriptions........................1374 25.5.1.1 PEX_LUT Memory map......................1374 25.5.1.2 PEX LUT Status Register (PEXLSR)..................1376 25.5.1.2.1 Offset........................1376 25.5.1.2.2 Function......................1377 25.5.1.2.3 Diagram.......................1377 25.5.1.2.4 Fields........................1377 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 97 PEX LUT Entry a Lower Data Register (PEXL1LDR - PEXL31LDR)........1382 25.5.1.7.1 Offset........................1382 25.5.1.7.2 Function......................1382 25.5.1.7.3 Diagram.......................1382 25.5.1.7.4 Fields........................1382 25.5.1.8 PEX PFa Config Register (PEX_PF0_CONFIG)..............1383 25.5.1.8.1 Offset........................1383 25.5.1.8.2 Function......................1383 25.5.1.8.3 Diagram.......................1383 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 98 PEX PFa PCIE message command register (PEX_PF0_MCR)..........1389 25.5.1.13.1 Offset........................1390 25.5.1.13.2 Function......................1390 25.5.1.13.3 Diagram.......................1390 25.5.1.13.4 Fields........................1390 25.5.1.14 PEX PFa Route By Port Address Upper register (PEX_PF0_RBP_ADDR_U)....... 1391 25.5.1.14.1 Offset........................1391 25.5.1.14.2 Function......................1391 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 99 25.5.1.18.4 Fields........................1396 25.6 Functional Description..............................1398 25.6.1 Architecture..............................1399 25.6.1.1 PCI Express Transactions......................1399 25.6.1.2 Transaction ordering rules......................1400 25.6.1.3 Internal Address Translation Unit....................1401 25.6.1.3.1 iATU Overview....................1401 25.6.1.3.2 Programming the iATU..................1402 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 100 Inbound Messages....................1415 25.6.1.8 Error Handling........................... 1416 25.6.1.8.1 PCI Express Error Logging and Signaling............1416 25.6.2 Interrupts................................ 1417 25.6.3 Initial Credit Advertisement...........................1418 25.6.4 Power Management............................1418 25.6.4.1 L2/L3 Ready Link State......................1419 25.6.5 Hot Reset................................1419 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 101 Register Write Access............................ 1433 26.4.2 Peripheral Bus Register Descriptions......................1434 26.4.2.1 Module Configuration Register (QuadSPI_MCR)..............1440 26.4.2.2 IP Configuration Register (QuadSPI_IPCR)................1443 26.4.2.3 Flash Configuration Register (QuadSPI_FLSHCR)..............1443 26.4.2.4 Buffer0 Configuration Register (QuadSPI_BUF0CR).............. 1444 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 102 Flash memory mapped AMBA bus..........................1474 26.5.1 AHB Bus Access Considerations........................1474 26.5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A............. 1475 26.5.3 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)................1476 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 103 Exclusive Access to Serial Flash for AHB Commands................. 1497 26.8.3.1 RX Buffer Read via QSPI_ARDB Registers................1498 26.8.3.2 RX Buffer Read via QSPI_RBDR Registers................1498 26.8.4 Command Arbitration ........................... 1499 26.8.5 Flash Device Selection...........................1499 26.8.6 DMA Usage..............................1500 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 104 26.11.2.1 SDR mode..........................1510 26.11.2.1.1 Internal sampling....................1510 26.11.2.1.2 DQS sampling method..................1511 26.11.2.2 DDR Mode..........................1512 26.11.2.2.1 DQS sampling method..................1512 26.11.3 Data Strobe (DQS) sampling method......................1512 26.11.3.1 Basic Description........................1512 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 105 Function............................. 1523 27.3.4.3 Diagram............................1523 27.3.4.4 Fields............................1523 27.3.5 Command completion coalescing control register (CCC_CTL)..............1524 27.3.5.1 Offset............................1524 27.3.5.2 Function............................. 1524 27.3.5.3 Diagram............................1524 27.3.5.4 Fields............................1524 27.3.6 HBA capabilities extended register (CAP2)....................1525 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 106 27.3.10 Port Phy3Cfg register (PP3C)........................1531 27.3.10.1 Offset............................1531 27.3.10.2 Function............................. 1531 27.3.10.3 Diagram............................1532 27.3.10.4 Fields............................1532 27.3.11 Port Phy4Cfg register (PP4C)........................1533 27.3.11.1 Offset............................1533 27.3.11.2 Function............................. 1533 27.3.11.3 Diagram............................1533 27.3.11.4 Fields............................1534 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 107 Fields............................1540 27.3.16 Port LinkCfg register (PLC).......................... 1541 27.3.16.1 Offset............................1541 27.3.16.2 Function............................. 1541 27.3.16.3 Diagram............................1541 27.3.16.4 Fields............................1542 27.3.17 Port LinkCfg1 register (PLC1)........................1543 27.3.17.1 Offset............................1543 27.3.17.2 Function............................. 1543 27.3.17.3 Diagram............................1543 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 108 Fields............................1549 27.3.22 Timer control register (TCR)......................... 1549 27.3.22.1 Offset............................1549 27.3.22.2 Function............................. 1550 27.3.22.3 Diagram............................1550 27.3.22.4 Fields............................1550 27.3.23 Port x command list base address register (PxCLB)..................1550 27.3.23.1 Offset............................1550 27.3.23.2 Diagram............................1551 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 109 Fields............................1557 27.3.29 Port x SATA status register (PxSSTS)......................1560 27.3.29.1 Offset............................1560 27.3.29.2 Function............................. 1560 27.3.29.3 Diagram............................1561 27.3.29.4 Fields............................1561 27.3.30 Port x SATA control register (PxSCTL)......................1561 27.3.30.1 Offset............................1562 27.3.30.2 Function............................. 1562 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 110 Command list structure......................1571 27.4.2.2 Vendor BIST command descriptor command FIS..............1572 27.4.2.3 Receive FIS area reg D2H RFIS structure................. 1572 27.5 PhyControl BIST modes............................... 1573 27.6 PHY control configuration register OOB timing setup....................1574 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 111 SerDes Module 28.1 The SerDes module as implemented on the chip......................1591 28.1.1 SerDes lane assignments and multiplexing....................1591 28.1.1.1 Configuration of networking SerDes..................1591 28.1.1.2 SerDes protocols........................1591 28.1.1.2.1 Disabling unused SerDes modules..............1593 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 112 SerDes PLLa Control Register 1 (PLL1CR1 - PLL2CR1)................1603 28.5.4.1 Offset............................1603 28.5.4.2 Function............................. 1603 28.5.4.3 Diagram............................1603 28.5.4.4 Fields............................1603 28.5.5 SerDes PLLa Control Register 5 (PLL1CR5 - PLL2CR5)................1604 28.5.5.1 Offset............................1604 28.5.5.2 Function............................. 1604 28.5.5.3 Diagram............................1604 28.5.5.4 Fields............................1605 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 113 28.5.10 General Control Register 0 (GR0)......................... 1611 28.5.10.1 Offset............................1611 28.5.10.2 Function............................. 1611 28.5.10.3 Diagram............................1611 28.5.10.4 Fields............................1611 28.5.11 Protocol Configuration Register 0 (PCCR0)....................1612 28.5.11.1 Offset............................1612 28.5.11.2 Function............................. 1612 28.5.11.3 Diagram............................1612 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 114 28.5.16 Speed Switch Control Register 0 - Lane a (LNASSCR0 - LNDSSCR0)............1623 28.5.16.1 Offset............................1623 28.5.16.2 Function............................. 1624 28.5.16.3 Diagram............................1624 28.5.16.4 Fields............................1624 28.5.17 Receive Equalization Control Register 0 - Lane a (LNARECR0 - LNDRECR0).........1627 28.5.17.1 Offset............................1627 28.5.17.2 Function............................. 1628 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 115 Fields............................1639 28.5.22 Test Control/Status Register 3 - Lane a (LNATCSR3 - LNDTCSR3)............1640 28.5.22.1 Offset............................1640 28.5.22.2 Function............................. 1640 28.5.22.3 Diagram............................1640 28.5.22.4 Fields............................1640 28.5.23 PEXA Protocol Control Register 0 (PEXACR0)...................1641 28.5.23.1 Offset............................1641 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 116 Function......................1647 28.6.1.2.3 Diagram.......................1647 28.6.1.2.4 Fields........................1648 28.6.1.3 KX PCS Status (KX_PCS_SR)....................1648 28.6.1.3.1 Offset........................1648 28.6.1.3.2 Function......................1649 28.6.1.3.3 Diagram.......................1649 28.6.1.3.4 Fields........................1649 28.6.1.4 KX PCS Device Identifier Upper (KX_PCS_DEV_ID)............1649 28.6.1.4.1 Offset........................1649 28.6.1.4.2 Function......................1650 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 117 28.6.1.8.2 Function......................1654 28.6.1.8.3 Diagram.......................1654 28.6.1.8.4 Fields........................1654 28.6.1.9 KX PCS Package Identifier Lower (KX_PCS_PKG_ID_L)............. 1654 28.6.1.9.1 Offset........................1654 28.6.1.9.2 Function......................1654 28.6.1.9.3 Diagram.......................1655 28.6.1.9.4 Fields........................1655 28.6.1.10 SGMII Control (C45_SGMII_CR).................... 1655 28.6.1.10.1 Offset........................1655 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 118 Function......................1660 28.6.1.14.3 Diagram.......................1660 28.6.1.14.4 Fields........................1661 28.6.1.15 SGMII Device Ability for SGMII (C45_SGMII_DEV_ABIL_SGMII)........1662 28.6.1.15.1 Offset........................1662 28.6.1.15.2 Function......................1662 28.6.1.15.3 Diagram.......................1662 28.6.1.15.4 Fields........................1662 28.6.1.16 SGMII Partner Ability for 1000Base-X (C45_SGMII_LP_DEV_ABIL_1KBX)....1663 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 119 28.6.1.20 SGMII LP Next Page Receive (C45_SGMII_NP_RX)............. 1668 28.6.1.20.1 Offset........................1668 28.6.1.20.2 Function......................1668 28.6.1.20.3 Diagram.......................1668 28.6.1.20.4 Fields........................1668 28.6.1.21 SGMII Extended Status (C45_SGMII_XTND_STAT).............1669 28.6.1.21.1 Offset........................1669 28.6.1.21.2 Function......................1669 28.6.1.21.3 Diagram.......................1669 28.6.1.21.4 Fields........................1670 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 120 SGMII IF Mode (C45_SGMII_IF_MODE)................1673 28.6.1.26.1 Offset........................1673 28.6.1.26.2 Function......................1673 28.6.1.26.3 Diagram.......................1673 28.6.1.26.4 Fields........................1673 28.6.2 MDIO_KX_AN register descriptions......................1674 28.6.2.1 MDIO_KX_AN Memory map....................1674 28.6.2.2 KX AN Control (KX_AN_CR)....................1675 28.6.2.2.1 Offset........................1675 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 121 28.6.2.6.2 Function......................1680 28.6.2.6.3 Diagram.......................1680 28.6.2.6.4 Fields........................1681 28.6.2.7 KX AN Devices in Package 1 (KX_AN_DEV_PRES1)............1681 28.6.2.7.1 Offset........................1682 28.6.2.7.2 Function......................1682 28.6.2.7.3 Diagram.......................1682 28.6.2.7.4 Fields........................1682 28.6.2.8 KX AN Package Identifier Upper (KX_AN_PKG_ID_H)............1683 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 122 KX AN Advertisement 2 (KX_AN_ADVERT2)..............1687 28.6.2.12.1 Offset........................1687 28.6.2.12.2 Function......................1687 28.6.2.12.3 Diagram.......................1687 28.6.2.12.4 Fields........................1687 28.6.2.13 KX AN LP Base Page Ability 0 (KX_AN_LP_BASE_PG_ABIL0)........1688 28.6.2.13.1 Offset........................1688 28.6.2.13.2 Function......................1688 28.6.2.13.3 Diagram.......................1688 28.6.2.13.4 Fields........................1688 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 123 KX AN XNP Transmit 2 (KX_AN_XNP_TX2)............... 1693 28.6.2.18.1 Offset........................1694 28.6.2.18.2 Function......................1694 28.6.2.18.3 Diagram.......................1694 28.6.2.18.4 Fields........................1694 28.6.2.19 KX AN LP XNP Ability 0 (KX_AN_LP_XNP_ABIL0)............1694 28.6.2.19.1 Offset........................1694 28.6.2.19.2 Function......................1694 28.6.2.19.3 Diagram.......................1695 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 124 28.6.2.23.3 Diagram.......................1699 28.6.2.23.4 Fields........................1699 28.6.3 MDIO_KX_VENDOR_SPEC register descriptions..................1699 28.6.3.1 MDIO_KX_VENDOR_SPEC Memory map................1699 28.6.3.2 KX Revision (KX_VND_REV)....................1700 28.6.3.2.1 Offset........................1700 28.6.3.2.2 Function......................1700 28.6.3.2.3 Diagram.......................1700 28.6.3.2.4 Fields........................1700 28.6.3.3 KX Scratch (KX_VND_SCRATCH)..................1701 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 125 KX AN Interrupt Mask (KX_VND_AN_INT_MSK)............... 1704 28.6.3.7.1 Offset........................1705 28.6.3.7.2 Function......................1705 28.6.3.7.3 Diagram.......................1705 28.6.3.7.4 Fields........................1705 28.6.4 MDIO_SGMII register descriptions......................1706 28.6.4.1 MDIO_SGMII Memory map..................... 1706 28.6.4.2 SGMII Control (SGMII_CR).....................1706 28.6.4.2.1 Offset........................1707 28.6.4.2.2 Function......................1707 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 126 Function......................1712 28.6.4.6.3 Diagram.......................1712 28.6.4.6.4 Fields........................1712 28.6.4.7 SGMII Device Ability for SGMII (SGMII_DEV_ABIL_SGMII)..........1713 28.6.4.7.1 Offset........................1713 28.6.4.7.2 Function......................1713 28.6.4.7.3 Diagram.......................1713 28.6.4.7.4 Fields........................1713 28.6.4.8 SGMII Partner Ability for 1000Base-X (SGMII_LP_DEV_ABIL_1KBX)......1714 28.6.4.8.1 Offset........................1714 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 127 SGMII LP Next Page Receive (SGMII_NP_RX)..............1719 28.6.4.12.1 Offset........................1719 28.6.4.12.2 Function......................1719 28.6.4.12.3 Diagram.......................1720 28.6.4.12.4 Fields........................1720 28.6.4.13 SGMII Extended Status (SGMII_XTND_STAT)..............1720 28.6.4.13.1 Offset........................1720 28.6.4.13.2 Function......................1721 28.6.4.13.3 Diagram.......................1721 28.6.4.13.4 Fields........................1721 28.6.4.14 SGMII Scratch (SGMII_SCRATCH)..................1721 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 128 SGMII IF Mode (SGMII_IF_MODE)..................1724 28.6.4.18.1 Offset........................1724 28.6.4.18.2 Function......................1724 28.6.4.18.3 Diagram.......................1725 28.6.4.18.4 Fields........................1725 28.7 Initialization/Application Information.......................... 1725 28.7.1 Initialization..............................1726 28.7.1.1 1G SGMII..........................1726 28.7.1.2 2.5G SGMII..........................1726 28.7.1.3 1000Base-KX..........................1727 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 129 Arm generic interrupt controller (GIC)......................1740 29.5.6 TrustZone Watchdog (TrustZone WDOG)....................1740 29.5.7 On-Chip RAM (OCRAM)..........................1741 29.5.8 Secure debug controller..........................1741 29.5.9 SEC 5.5................................1742 29.5.10 Internal boot ROM and ISBC........................1744 29.5.11 External tamper-detection..........................1745 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 130 Debug Response Value Register n (SFP_DRVRn)..............1766 29.8.3.9 Factory Section Write Protect Register (SFP_FSWPR)............1767 29.8.3.10 Factory Unique ID Register n (SFP_FUIDRn)................1768 29.8.3.11 ISBC Configuration Register (SFP_ISBCCR)................1769 29.8.3.12 Factory Scratch Pad Fuse Register n (SFP_FSPFRn)..............1770 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 131 SecMon_HP Security Interrupt Control Register (HPSICR).............1782 29.9.4.4.1 Offset........................1782 29.9.4.4.2 Function......................1782 29.9.4.4.3 Diagram.......................1782 29.9.4.4.4 Fields........................1783 29.9.4.5 SecMon_HP Security Violation Control Register (HPSVCR)..........1784 29.9.4.5.1 Offset........................1784 29.9.4.5.2 Function......................1784 29.9.4.5.3 Diagram.......................1784 29.9.4.5.4 Fields........................1784 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 132 SecMon_LP Power Glitch Detector Register (LPPGDR)............1791 29.9.4.10.1 Offset........................1791 29.9.4.10.2 Function......................1791 29.9.4.10.3 Diagram.......................1791 29.9.4.10.4 Fields........................1792 29.9.4.11 SecMon_HP Version ID Register 1 (HPVIDR1)..............1792 29.9.4.11.1 Offset........................1792 29.9.4.11.2 Function......................1792 29.9.4.11.3 Diagram.......................1792 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 133 LS1012A SPI signals............................. 1805 30.1.3 LS1012A SPI module special consideration....................1805 30.1.4 SPI_MCR register mapping........................... 1806 30.2 Introduction...................................1806 30.2.1 Block Diagram............................... 1806 30.2.2 Features................................1807 30.2.3 Interface configurations..........................1809 30.2.3.1 SPI configuration........................1809 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 134 Offset............................1816 30.4.3.2 Function............................. 1816 30.4.3.3 Diagram............................1816 30.4.3.4 Fields............................1817 30.4.4 Clock and Transfer Attributes Register (In Master Mode) (CTAR0 - CTAR3)..........1817 30.4.4.1 Offset............................1817 30.4.4.2 Function............................. 1817 30.4.4.3 Diagram............................1818 30.4.4.4 Fields............................1818 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 135 Transmit FIFO Registers (TXFR0 - TXFR15)....................1830 30.4.9.1 Offset............................1830 30.4.9.2 Function............................. 1831 30.4.9.3 Diagram............................1831 30.4.9.4 Fields............................1831 30.4.10 Receive FIFO Registers (RXFR0 - RXFR15)....................1831 30.4.10.1 Offset............................1831 30.4.10.2 Function............................. 1832 30.4.10.3 Diagram............................1832 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 136 30.5.3.1 Baud rate generator........................1842 30.5.3.2 PCS to SCK Delay (tCSC)......................1842 30.5.3.3 After SCK Delay (tASC)......................1843 30.5.3.4 Delay after Transfer (tDT)......................1843 30.5.3.5 Peripheral Chip Select Strobe Enable (PCSS_b)............... 1844 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 137 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO......1860 30.6.5.2 Address Calculation for the First-in Entry and Last-in Entry in the CMD FIFO...... 1860 30.6.5.3 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO......1861 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 138 Fields............................1871 31.3.4 TMU monitor temperature measurement interval register (TMTMIR)............1872 31.3.4.1 Offset............................1872 31.3.4.2 Function............................. 1872 31.3.4.3 Diagram............................1873 31.3.4.4 Fields............................1873 31.3.5 TMU interrupt enable register (TIER)......................1874 31.3.5.1 Offset............................1874 31.3.5.2 Function............................. 1874 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 139 Fields............................1879 31.3.10 TMU monitor low temperature capture register (TMLTCR)................ 1880 31.3.10.1 Offset............................1880 31.3.10.2 Function............................. 1880 31.3.10.3 Diagram............................1880 31.3.10.4 Fields............................1880 31.3.11 TMU monitor high temperature immediate threshold register (TMHTITR)..........1881 31.3.11.1 Offset............................1881 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 140 Fields............................1886 31.3.16 TMU report immediate temperature site register 0 (TRITSR0)..............1887 31.3.16.1 Offset............................1887 31.3.16.2 Function............................. 1887 31.3.16.3 Diagram............................1887 31.3.16.4 Fields............................1887 31.3.17 TMU report average temperature site register 0 (TRATSR0)............... 1888 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 141 31.3.21 TMU temperature range 3 control register (TTR3CR).................. 1893 31.3.21.1 Offset............................1893 31.3.21.2 Function............................. 1894 31.3.21.3 Diagram............................1894 31.3.21.4 Fields............................1894 31.4 Functional Description..............................1895 31.4.1 Monitoring..............................1895 31.4.2 Reporting................................1896 Chapter 32 Universal Serial Bus Interface 2.0 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 142 32.3.4.2 Function............................. 1905 32.3.4.3 Diagram............................1905 32.3.4.4 Fields............................1905 32.3.5 Capability Register Length (CAPLENGTH)....................1906 32.3.5.1 Offset............................1906 32.3.5.2 Function............................. 1906 32.3.5.3 Diagram............................1906 32.3.5.4 Fields............................1907 32.3.6 Host Controller Interface Version Number (HCIVERSION)................1907 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 143 32.3.10 Device Controller Capability Parameters (DCCPARAMS)................1912 32.3.10.1 Offset............................1912 32.3.10.2 Function............................. 1912 32.3.10.3 Diagram............................1912 32.3.10.4 Fields............................1913 32.3.11 USB Command (USBCMD)..........................1913 32.3.11.1 Offset............................1913 32.3.11.2 Function............................. 1914 32.3.11.3 Diagram............................1914 32.3.11.4 Fields............................1914 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 144 32.3.16 Periodic Frame List Base Address [host mode] (PERIODICLISTBASE)............ 1925 32.3.16.1 Offset............................1925 32.3.16.2 Function............................. 1926 32.3.16.3 Diagram............................1926 32.3.16.4 Fields............................1926 32.3.17 Next Asynchronous List Addr [host mode] (ASYNCLISTADDR).............. 1927 32.3.17.1 Offset............................1927 32.3.17.2 Function............................. 1927 32.3.17.3 Diagram............................1927 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 145 Fields............................1934 32.3.22 Endpoint NAK Indicaton Register (ENDPTNAK)..................1935 32.3.22.1 Offset............................1935 32.3.22.2 Function............................. 1935 32.3.22.3 Diagram............................1935 32.3.22.4 Fields............................1936 32.3.23 Endpoint NAK Indication Enable Register (ENDPTNAKEN)..............1936 32.3.23.1 Offset............................1937 32.3.23.2 Function............................. 1937 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 146 32.3.27.1 Offset............................1948 32.3.27.2 Function............................. 1948 32.3.27.3 Diagram............................1948 32.3.27.4 Fields............................1949 32.3.28 Endpoint Initialization (ENDPOINTPRIME)....................1949 32.3.28.1 Offset............................1949 32.3.28.2 Function............................. 1949 32.3.28.3 Diagram............................1949 32.3.28.4 Fields............................1950 32.3.29 Endpoint Flush (ENDPTFLUSH)........................1950 32.3.29.1 Offset............................1950 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 147 Offset............................1956 32.3.33.2 Function............................. 1956 32.3.33.3 Diagram............................1956 32.3.33.4 Fields............................1957 32.3.34 Snoop n (SNOOP1 - SNOOP2)........................1959 32.3.34.1 Offset............................1959 32.3.34.2 Function............................. 1959 32.3.34.3 Diagram............................1959 32.3.34.4 Fields............................1960 32.3.35 Age Count Threshold (AGE_CNT_THRESH)....................1961 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 148 FIFO RAM controller............................ 1968 32.4.4 PHY interface..............................1968 32.5 Host data structures...............................1969 32.5.1 Periodic frame list............................1969 32.5.2 Asynchronous list queue head pointer......................1971 32.5.3 Isochronous (high-speed) transfer descriptor (iTD)..................1972 32.5.3.1 Next link pointer-iTD.........................1973 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 149 Power port..............................1993 32.6.3 Reporting over-current........................... 1994 32.6.4 Suspend/resume ............................1994 32.6.4.1 Port suspend/resume........................1995 32.6.5 Schedule traversal rules..........................1997 32.6.6 Periodic schedule frame boundaries vs. bus frame boundaries..............1998 32.6.7 Periodic schedule............................2001 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 150 Tracking split transaction progress for interrupt transfers .........2031 32.6.12.2.5 Split transaction execution state machine for interrupt ........2032 32.6.12.2.6 Periodic interrupt-do-start-split ................2033 32.6.12.2.7 Periodic interrupt-do-complete-split ..............2034 32.6.12.2.8 Managing the QH[FrameTag] field ..............2038 32.6.12.2.9 Rebalancing the periodic schedule ..............2039 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 151 32.7.1 Endpoint queue head............................2064 32.7.1.1 Endpoint capabilities/characteristics ..................2065 32.7.1.2 Transfer overlay ........................2066 32.7.1.3 Current dTD pointer........................2066 32.7.1.4 Setup buffer..........................2067 32.7.2 Endpoint transfer descriptor (dTD)........................2067 32.8 Device operational model............................. 2070 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 152 Isochronous endpoint operational model................... 2084 32.8.3.6.1 Isochronous pipe synchronization...............2086 32.8.3.6.2 Isochronous endpoint bus response matrix............2086 32.8.4 Managing queue heads...........................2087 32.8.4.1 Queue head initialization......................2087 32.8.4.2 Operational model for setup transfers..................2088 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 153 Multiple transaction translators................2099 32.9.2 Device operation............................2099 32.9.3 Non-zero fields the register file........................2099 32.9.4 SOF interrupt..............................2100 32.9.5 Embedded design............................2100 32.9.5.1 Frame adjust register........................2100 32.9.6 Miscellaneous variations from EHCI......................2100 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 154 Offset............................2112 33.2.4.2 Diagram............................2112 33.2.4.3 Fields............................2112 33.2.5 Host controller structural parameters 3 (HCSPARAMS3)................2113 33.2.5.1 Offset............................2113 33.2.5.2 Diagram............................2113 33.2.5.3 Fields............................2113 33.2.6 Host controller capability parameters 1 (HCCPARAMS1)................2114 33.2.6.1 Offset............................2114 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 155 33.2.11 Global SoC bus configuration register 1 (GSBUSCFG1)................2123 33.2.11.1 Offset............................2123 33.2.11.2 Function............................. 2124 33.2.11.3 Diagram............................2124 33.2.11.4 Fields............................2124 33.2.12 Global Tx threshold control register (GTXTHRCFG).................. 2125 33.2.12.1 Offset............................2125 33.2.12.2 Function............................. 2125 33.2.12.3 Diagram............................2125 33.2.12.4 Fields............................2126 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 156 Diagram............................2138 33.2.17.4 Fields............................2139 33.2.18 Global user control register (GUCTL)......................2139 33.2.18.1 Offset............................2139 33.2.18.2 Function............................. 2139 33.2.18.3 Diagram............................2139 33.2.18.4 Fields............................2140 33.2.19 Global SoC bus error address register low (GBUSERRADDRLO)..............2142 33.2.19.1 Offset............................2142 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 157 33.2.23.2 Diagram............................2147 33.2.23.3 Fields............................2147 33.2.24 Global hardware parameters register 1 (GHWPARAMS1)................2148 33.2.24.1 Offset............................2148 33.2.24.2 Function............................. 2148 33.2.24.3 Diagram............................2149 33.2.24.4 Fields............................2149 33.2.25 Global hardware parameters register 2 (GHWPARAMS2)................2151 33.2.25.1 Offset............................2151 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 158 33.2.31 Global high-speed port to bus instance mapping register - low (GPRTBIMAP_HSLO)......2161 33.2.31.1 Offset............................2161 33.2.31.2 Function............................. 2161 33.2.31.3 Diagram............................2162 33.2.31.4 Fields............................2162 33.2.32 Global high-speed port to bus instance mapping register - high (GPRTBIMAP_HSHI)......2162 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 159 33.2.36 Global receive FIFO size register (GRXFIFOSIZ_0 - GRXFIFOSIZ_2)............. 2170 33.2.36.1 Offset............................2170 33.2.36.2 Function............................. 2170 33.2.36.3 Diagram............................2171 33.2.36.4 Fields............................2171 33.2.37 Global event buffer address (low) register (GEVNTADRLO)..............2171 33.2.37.1 Offset............................2171 33.2.37.2 Function............................. 2172 33.2.37.3 Diagram............................2172 33.2.37.4 Fields............................2172 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 160 33.2.42 Global device TXFIFO DMA priority register (GTXFIFOPRIDEV)............2177 33.2.42.1 Offset............................2177 33.2.42.2 Function............................. 2177 33.2.42.3 Diagram............................2177 33.2.42.4 Fields............................2178 33.2.43 Global host TXFIFO DMA priority register (GTXFIFOPRIHST)............... 2178 33.2.43.1 Offset............................2178 33.2.43.2 Function............................. 2178 33.2.43.3 Diagram............................2179 33.2.43.4 Fields............................2179 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 161 Fields............................2186 33.2.48 Device control register (DCTL)........................2187 33.2.48.1 Offset............................2187 33.2.48.2 Function............................. 2187 33.2.48.3 Diagram............................2188 33.2.48.4 Fields............................2188 33.2.49 Device event enable register (DEVTEN).......................2191 33.2.49.1 Offset............................2191 33.2.49.2 Function............................. 2192 33.2.49.3 Diagram............................2192 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 162 33.2.54 Device physical endpoint-n command parameter 2 register (DEPCMDPAR2_0 - DEPCMDPAR2_7)..2202 33.2.54.1 Offset............................2202 33.2.54.2 Function............................. 2202 33.2.54.3 Diagram............................2202 33.2.54.4 Fields............................2202 33.2.55 Device physical endpoint-n command parameter 1 register (DEPCMDPAR1_0 - DEPCMDPAR1_7)..2203 33.2.55.1 Offset............................2203 33.2.55.2 Function............................. 2203 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 163 Function............................. 2210 33.2.59.3 Diagram............................2210 33.2.59.4 Fields............................2210 33.2.60 OTG events register (OEVT)......................... 2211 33.2.60.1 Offset............................2211 33.2.60.2 Function............................. 2212 33.2.60.3 Diagram............................2212 33.2.60.4 Fields............................2212 33.2.61 OTG events enable register (OEVTEN)......................2214 33.2.61.1 Offset............................2214 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 164 Fields............................2222 33.2.66 ADP event enable register (ADPEVTEN).....................2223 33.2.66.1 Offset............................2223 33.2.66.2 Diagram............................2224 33.2.66.3 Fields............................2224 33.3 USB PHY SuperSpeed register descriptions........................ 2225 33.3.1 USB_PHY_SS Memory map.........................2225 33.3.2 SUP_IDCODE_LO (IP_IDCODE_LO)......................2225 33.3.2.1 Offset............................2225 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 165 Interrupt on Short Packet (ISP) and Continue on Short Packet (CSP) Usage..2242 33.4.2.1.6 Example of Setting Up TRBs................2242 33.4.3 Device Programming Model.......................... 2246 33.4.3.1 Register Initialization......................... 2246 33.4.3.1.1 Device Power-On or Soft Reset................2247 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 166 Handling ENDPOINT_HALT................2269 33.4.3.2.7 Handling L1 Event During a Transfer..............2269 33.4.3.3 Isochronous Transfer Programming Model................2269 33.4.3.3.1 Definitions......................2270 33.4.3.3.2 Endpoint configuration..................2271 33.4.3.3.3 Transfer configuration..................2271 33.4.3.3.4 Starting a Transfer....................2272 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 167 Host programming model..........................2290 33.4.4.1 Initializing host registers......................2290 33.4.4.2 Host controller capability registers.................... 2290 33.4.4.3 xHCI implementation details..................... 2290 33.4.4.3.1 LHCRST behavior....................2291 33.4.4.3.2 ENT requirements....................2291 33.4.4.3.3 Behavior on babble error..................2291 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 168 33.4.6.1.4.5 Programming flow for OTG in USB 3.0........2308 33.4.6.1.5 Common driver tasks..................2310 33.4.6.1.6 A-device flow......................2315 33.4.6.1.7 SRP detection by the core (Timeline for ADevSRPDetEvnt)......2321 33.4.6.1.8 VBUS turned ON by the core (Timeline for ADevBSessEndEvnt)....2321 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 169 Interrupt event ............................... 2336 34.3.3 Operations..............................2336 34.3.3.1 Watchdog reset generation......................2336 34.3.4 Reset (PORESET)............................2336 34.3.5 Interrupt................................2337 34.3.6 Flow Diagrams............................... 2337 34.4 Initialization.................................. 2339 34.5 WDOG Memory Map/Register Definition........................2340 34.5.1 Watchdog Control Register (WDOGx_WCR)....................2340 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 170 Section number Title Page 34.5.2 Watchdog Service Register (WDOGx_WSR)....................2342 34.5.3 Watchdog Reset Status Register (WDOGx_WRSR)..................2342 34.5.4 Watchdog Interrupt Control Register (WDOGx_WICR)................2343 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 171 RGMII, and SGMII that can accommodate 2.5G Ethernet PHYs. To deliver outstanding security performance, the device features a hardware-based acceleration engine to support secure boot, and networking with both Arm TrustZone and NXP’s QorIQ Trust Architecture. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 172 • Packet Forwarding Engine (PFE) • Cryptography acceleration (SEC) • Ethernet interfaces supported by PFE: • Two quad-speed Ethernet MACs supporting 2.5G, 1G, 100M, 10M • Supports RGMII, SGMII 1G, SGMII 2.5G QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 173 • Single-source clocking solution enabling generation of core, platform, DDR, SerDes, and USB clocks from a single external crystal and internal crystal oscillator • Thermal monitor unit (TMU) with +/- 3°C accuracy • Two WatchDog timers • Arm generic timer QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 174 LS1012A OCRAM UART SD 3.0 ENET SAI / I RJ45 UART 4-wire PCle PCle 2.0 a b g SATA 3.0 3.0/2.0 QuadSPI DDR3L FLASH Figure 1-2. Entry-level broadband Ethernet gateway QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 175 • USB 3.0 to support LTE/4G wireless broadband backhaul or super-fast direct attachment. • SATA 3.0 to support high-speed data streaming to both disk-based or solid-state storage media devices. • Dual SD/MMC enables configuration for small media storage or low-bandwidth wireless connectivity. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 176 LS1012A OCRAM UART SD 3.0 ENET SAI / I RJ45 UART 4-wire PCle PCle 2.0 a b g SATA 3.0 3.0/2.0 DDR3L QuadSPI FLASH Figure 1-3. Consumer NAS/DAS with optional Wi-Fi QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 177 • Dual Ethernet controllers, which can be configured as the first controller supporting 2.5G SGMII PHY and the second controller supporting 1G RGMII PHY. • SATA 3.0 to support high-speed data streaming to both disk-based or solid-state storage media devices. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 178 • SATA 3.0 to support for high-speed data streaming to both disk-based or solid-state storage media devices. • Dual SD/MMC enables configuration for small media storage or low-bandwidth wireless audio streaming. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 179 SGTL5000 4-wire PCle 2.0 SATA 3.0 KWxx 6Lowpan DDR3L QuadSPI FLASH RF Tx/Rx 802.15.4 SRAM 2.4 GHz FLASH 6-bit Temperature 16-bit Wind speed Rain Figure 1-7. IoT gateway with audio networking QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 180 • Data coherency between the Cortex-A53 core and all I/O masters with three independent Points-of-Serialization (PoS) and full barrier support high-bandwidth, interconnect functionality between the masters and up to three slaves QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 181 • 32 channels support independent 8-, 16- or 32-bit single value or block transfers • Supports variable sized queues and circular queues • Source and destination address registers are independently configured to post increment or remain constant QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 182 • Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs • Deadtime insertion is available for each complementary pair • Generation of hardware triggers QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 183 The USB 2.0 controller with ULPI interface provides point-to-point connectivity that complies with the USB specification, Rev. 2.0. The device doesn't have an integrated PHY for this USB 2.0 controller and instead supports external PHY with ULPI interface. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 184 • Native command queuing • Staggered spin-up • Port multiplier support • Standard ATA master-only emulation • Supports ATA shadow registers • SATA superset registers • SError, SControl, SStatus • Interrupt driven QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 185 S/SAI module provides the following features: • Transmitter with independent bit clock and frame sync supporting a data line • Receiver with independent bit clock and frame sync supporting a data line QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 186 SD (SD cards/SDIO cards/embedded SDIO) SD memory card SDIO card eSDIO MMC/ eMMC eMMC DDR eMMC FS/HS/HS200 NOTE For maximum speed supported on each interface, refer to Device data sheet and AN5192. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 187 C is integrated with eDMA and allows communication between a number of devices. LS1012A supports two I C controllers. 1.4.15 Quad serial peripheral interface (QuadSPI) The QuadSPI is integrated with eDMA and has the following general features: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 188 RTC 32 KHz clock and module clock (platform clock). LS1012A supports two WDOG timers. Out of two WDOGs, one is dedicated for TrustZone support and another is for A53 core. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 189 Module name Size Accessible with x-bit addressing (hex) 0_0000 Secure boot ROM 1 MB 10_0000 Extended Boot 15 MB 100_0000 CCSR register 240 MB space Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 190 20_0000_0000 Reserved 128 GB 40_0000_0000 PCI Express 1 (I/O, 32 GB config and memory space) 48_0000_0000 Reserved 32 GB 50_0000_0000 Reserved 192 GB 80_0000_0000 Reserved 32 GB 88_0000_0000 Reserved 480 GB QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 191 159_0000-160_FFFF Reserved 161_0000-161_FFFF Little-endian (byte swapping not required) 162_0000-16F_FFFF Reserved 170_0000-17F_FFFF Big-endian (byte swapping Refer chip security reference required) manual for details. 180_0000-1E7_FFFF Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 192 2AE_0000-2AE_FFFF WDOG2 Big-endian (byte swapping required) 2AF_0000-2AF_FFFF Reserved 2B0_0000-2B0_FFFF System counter (secure) Big-endian (byte swapping required) 2B1_0000-2B1_FFFF System counter (non-secure) Big-endian (byte swapping required) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 193 850_0000-85F_FFFF Reserved 860_0000-860_FFFF USB2 controller Big-endian (byte swapping required) 861_0000-FFF_FFFF Reserved 1. Datapath components should be in mixed endianness. PFE and Security module data structures can be in the following locations: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 194 • Arm A53, big-endian mode: Datapath software (at A53) does not perform endianness-related byte-swap for accessing the datapath components. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 195 • Clock and JTAG signals • Power-on-Reset configuration signals • QuadSPI interface signals • FlexTimer module interface signals • SAI/I2S module interface signals • USB controller interface (USB) signals QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 196 D1_MCAS_B Column Address Strobe D1_MCK Clock D1_MCKE Clock Enable D1_MCK_B Clock Complement D1_MCS_B Chip Select D1_MDIC Driver Impedence Calibration D1_MDM0 Data Mask D1_MDM1 Data Mask Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 197 GPIO1_07 SAI5_TX_DATA SAI5_RX_DATA UART2_SIN Receive Data GPIO1_06 UART2_SOUT Transmit Data GPIO1_08 IIC1 (See IIC External Signal Descriptions for more details.) IIC1_SCL Serial Clock GPIO1_02 FTM1_CH0 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 198 Master in slave out SDHC2_DAT3 GPIO1_28 FTM2_CH1 SAI1_RX_BCLK SPI_MOSI Master out slave in SDHC2_CMD GPIO1_24 FTM1_CH1 SAI1_RX_DATA eSDHC 1 (See eSDHC External Signal Descriptions for more details.) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 199 USB1_PWRFAULT ASLEEP ASLEEP GPIO2_01 PORESET_B Power On Reset QSPI_A_DATA3 RESET_REQ_B Reset Request GPIO1_14 IIC2_SDA RESET_REQ_B Reset Request GPIO1_31 cfg_rcw_src CLK_OUT TA_TMP_DETECT_B Tamper Detect GPIO2_17 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 200 SD1_RX2_N SerDes Receive Data (negative) SD1_RX2_P SerDes Receive Data (positive) SD1_TX0_N SerDes Transmit Data (negative) SD1_TX0_P SerDes Transmit Data (positive) SD1_TX1_N SerDes Transmit Data (negative) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 201 EC1_TXD0 USB2_D3 USB Data GPIO2_05 SAI2_RX_DATA USB2_D4 USB Data EC1_GTX_CLK GPIO2_07 SAI2_TX_BCLK EC1_RX_CLK USB2_D5 USB Data GPIO2_13 SAI4_TX_SYNC SAI4_RX_SYNC USB2_D6 USB Data EC1_RXD3 GPIO2_09 SAI2_RX_SYNC Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 202 EC1_RX_CLK Receive Clock GPIO2_13 SAI4_TX_SYNC SAI4_RX_SYNC USB2_D5 EC1_RX_DV Receive Data Valid GPIO2_14 SAI4_TX_BCLK SAI4_RX_BCLK USB2_DIR EC1_TXD0 Transmit Data GPIO2_05 SAI2_RX_DATA USB2_D3 EC1_TXD1 Transmit Data GPIO2_04 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 203 GPIO1_09 General Purpose Input/Output UART2_CTS_B SAI5_TX_SYNC SAI5_RX_SYNC GPIO1_10 General Purpose Input/Output TRST_B SAI5_TX_BCLK SAI5_RX_BCLK QSPI_A_DATA0 GPIO1_11 General Purpose Input/Output cfg_eng_use2 QSPI_A_DATA1 GPIO1_12 General Purpose Input/Output Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 204 SAI1_TX_DATA SPI_CLK GPIO1_30 General Purpose Input/Output TBSCAN_EN_B FTM_EXTCLK CLK_OUT GPIO1_31 General Purpose Input/Output cfg_rcw_src RESET_REQ_B GPIO2_00 General Purpose Input/Output USB1_DRVVBUS USB1_PWRFAULT GPIO2_01 General Purpose Input/Output Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 205 EMI1_MDC GPIO2_15 General Purpose Input/Output EMI1_MDIO GPIO2_16 General Purpose Input/Output TA_TMP_DETECT GPIO2_17 General Purpose Input/Output Power-On-Reset Configuration (See Reset Configuration Signal Descriptions for more details.) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 206 FTM2_CH3 Channel 3 SDHC2_CLK GPIO1_29 SAI1_TX_DATA SPI_CLK Synchronous Audio Interfaces (See SAI External Signal Descriptions for more details.) SAI1_RX_BCLK SAI Receive Clock SDHC2_DAT3 GPIO1_28 FTM2_CH1 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 207 SAI Receive Clock EC1_RXD0 SAI3_TX_BCLK GPIO2_12 USB2_STP EC1_TXD2 SAI3_RX_DATA / SAI Receive Data SAI3_TX_DATA GPIO2_03 USB2_D1 EC1_RXD1 SAI3_RX_SYNC / SAI Receive Sync SAI3_TX_SYNC GPIO2_11 USB2_NXT Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 208 SAI Transmit Data SAI5_RX_DATA GPIO1_07 UART2_RTS_B SAI5_TX_SYNC / SAI Transmit Sync SAI5_RX_SYNC GPIO1_09 UART2_CTS_B NOTE Refer Differences between silicon revisions 1.0 and 2.0 for the signal multiplexing changes in silicon revision 1.0. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 209 (rather than at the block level) typically by a reset configuration word (RCW) option. For example, the signal QSPI_A_DATA[2:3]/ QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 210 Reserved EC1_RXD3 GPIO2[9] SAI2_RX_SYNC EC1_RXD3 USB2_D6 Reserved EC1_RXD2 GPIO2[10] SAI2_RX_BCLK EC1_RXD2 USB2_D7 Reserved RCW[EC1_EXT_SAI2_TX] RCW[EC1_BASE] EC1_TXD1 GPIO2[4] SAI2_TX_DATA EC1_TXD1 USB2_D2 Reserved EC1_TX_EN GPIO2[6] SAI2_TX_SYNC EC1_TX_EN Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 211 Reserved EC1_RXD1 USB2_NXT Reserved EC1_RXD0 GPIO2[12] SAI3_TX_BCLK SAI3_RX_BCLK Reserved EC1_RXD0 USB2_STP Reserved RCW[EC1_EXT_SAI4] RCW[EC1_BASE] EC1_TXD3 GPIO2[2] SAI4_TX_DATA SAI4_RX_DATA Reserved EC1_TXD3 USB2_D0 Reserved EC1_RX_CLK GPIO2[13] SAI4_TX_SYNC Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 212 EMI1_MDIO GPIO2[16] EMI1_MDIO 3.4.3 eSDHC1 and GPIO1 signal multiplexing The eSDHC1 interface shares signals with GPIO1. The functionality of these signals are determined by the RCW[SDHC1_BASE], RCW[SDHC1_CD], RCW[SDHC1_WP], and RCW[SDHC1_VSEL] fields. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 213 GPIO1[17] SDHC1_DAT1 SDHC1_CLK Reserved SDHC1_DAT2 GPIO1[18] SDHC1_DAT2 GPIO1[18] Reserved SDHC1_DAT3 GPIO1[19] SDHC1_DAT3 GPIO1[19] Reserved SDHC1_CLK GPIO1[20] SDHC1_CLK GPIO1[20] Reserved RCW[SDHC1_CD] SDHC1_CD_B GPIO1[21] SDHC1_CD_B RCW[SDHC1_WP] SDHC1_WP GPIO1[22] SDHC1_WP RCW[SDHC1_VSEL] SDHC_VSEL GPIO1[23] SDHC1_VSEL QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 214 RCW[SDHC2_EXT_ RCW[SDHC2_BASE_DAT321] DAT1] SDHC2_DAT1 GPIO1[26] FTM2_CH2 SDHC2_DAT1 SAI1_TX_SYNC SPI_CS1_B RCW[SDHC2_EXT_ RCW[SDHC2_BASE_BASE] CMD] SDHC2_CMD GPIO1[24] FTM1_CH1 SDHC2_CMD SAI1_RX_DATA SPI_MOSI RCW[SDHC2_EXT_ RCW[SDHC2_BASE_BASE] DAT0] SDHC2_DAT0 GPIO1[25] FTM1_CH3 SDHC2_DAT0 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 215 C1 interface shares signals with GPIO1 and FTM. The functionality of these signals is determined by the RCW[IIC1_BASE]. Table 3-8. I C1 signal configuration Signal name Signal function RCW[IIC1_BASE] IIC1_SCL GPIO1[2] IIC1_SCL FTM1_CH0 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 216 RCW[QSPI_DATA1_GPIO] / RCW[QSPI_IIC2] RCW[QSPI_DATA0_GPIO] QSPI_A_DATA0 QSPI_A_DATA0 GPIO1[11] QSPI_A_SCK QSPI_A_SCK GPIO1[4] QSPI_A_CS0 QSPI_A_CS0 GPIO1[5] RCW[QSPI_DATA1_GPIO] QSPI_A_DATA1 QSPI_A_DATA1 GPIO1[12] Reserved Reserved RCW[QSPI_IIC2] QSPI_A_DATA2 GPIO1[13] IIC2_SCL QSPI_A_DATA2 GPIO1[13] Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 217 The functionality of these signals is determined by the RCW[UART2_BASE_DATA] and RCW[UART2_BASE_FLOW]). Table 3-11. UART2 signal configuration Signal name Signal function RCW[UART2_BASE_DATA] / RCW[UART2_BASE_FLOW] RCW[UART2_BASE_DATA] GPIO1[8] UART2_SOUT GPIO1[6] UART2_SIN RCW[UART2_BASE_FLOW] GPIO1[7] UART2_RTS_B Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 218 Reserved RCW[USB1_PWRFAULT _BASE] USB1_PWRFAULT GPIO2[1] USB1_PWRFAULT ASLEEP Reserved 3.4.11 TA_TMP_DETECT_B and GPIO2 signal multiplexing The TA_TMP_DETECT_B shares signals with GPIO2. The functionality of these signals is determined by the ITS fuse. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 219 (that is, after PORESET_B is deasserted). This is necessary to allow the interfaces to be used for fetching configuration information from non-volatile memory devices. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 220 Output Signal States During Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 221 NOTE: The following scenarios require RESET_REQ_B signal under which the system may not be recoverable: • Core watchdog expiry • Uncorrectable ECC errors • Boot and pre-boot errors Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 222 Asserted-An event has triggered a request for a power on reset. See Meaning the DCFG_RSTRQSR1 register in the DCFG chapter for more information. Negated-Indicates no reset request. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 223 Differences between silicon revisions 1.0 and 2.0 for the implementation in silicon revision 1.0. 4.2.2 External Clock Signals The table below describes some of the external clock signals of the chip. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 224 PLL cluster n general status register (PLLC1GSR) 0000_0000h A00h Platform clock domain control/status register (CLKPCSR) 0000_0000h C00h Platform PLL general status register (PLLPGSR) 0000_0000h 4.3.2 Core cluster n clock control/status register (CLKC1CSR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 225 Clock Select. Selects the clock source for the corresponding core cluster. See Table 4-5 above. 0000b - Corresponding cluster group PLL1 output 0001b - Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 226 4.3.3 PLL cluster n general status register (PLLC1GSR) 4.3.3.1 Offset Register Offset PLLC1GSR 800h 4.3.3.2 Function The PLLCnGSR registers provide information regarding the cluster PLL configuration. Table 4-6. PLL assignments to PLLCnGSR registers Register Cluster Group PLLC1GSR PLL1 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 227 All other encodings are reserved. NOTE: Not all ratios are supported due to frequency restrictions. Refer to the chip data sheet for the supported frequencies. — Reserved 4.3.4 Platform clock domain control/status register (CLKPCSR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 228 1b - Enable CLK_OUT pad 16-20 CLKOSEL CLKOSEL Selects core related clock signal for observation on CLK_OUT pad Settings not shown below are reserved. 11111b - 125 MHz SYSCLK Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 229 4.3.5 Platform PLL general status register (PLLPGSR) 4.3.5.1 Offset Register Offset PLLPGSR C00h 4.3.5.2 Function The PLLPGSR register provides information regarding the PLL's configuration. 4.3.5.3 Diagram Bits Reserved Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 230 1. A 25 MHz crystal is used with an on-chip crystal oscillator through pins (EXTAL/ XTAL) or an external clock oscillator/generator generates a 25 MHz square wave to EXTAL. See Clocking mode for details. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 231 512 bits). If the PBL reports an error during its process of loading the RCW data, the device reset sequence is halted indefinitely, waiting for another PORESET_B. 10. The platform clock tree is then switched over and is driven by the output of the platform PLL. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 232 SerDes PLLs results in RESET_REQ_B assertion, whether the system continues or halts is up to the board implementation as in RESET_REQ_B behavior Figure below shows a timing diagram of the POR sequence. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 233 4. In the core, corresponding ISR will be programmed with WFI 5. Core executes WFI instructions after receiving the interrupt. 6. Once the core executes WFI instruction, COP generates the corresponding core soft reset. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 234 In the following tables, the binary value 0 represents a signal pulled down to GND and a value of 1 represents a signal pulled up to that signal's corresponding V voltage level, regardless of the sense of the functional signal name. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 235 The chip uses an external memory interface to import a subset of the reset configuration information from a memory device during reset. Such information is called reset configuration word (RCW) data. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 236 01-11 Reserved SYS_PLL_RAT System PLL Multiplier/Ratio This field selects the platform clock:SYSCLK ratio. Options: 0_0000 Reserved 0_0100 4:1 (Asynchronous mode) All other encodings are reserved. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 237 OFF if the source is internal. If the source is external, the PLL1 cannot be powered OFF. Option : 0 PLL is not powered down 1 PLL is powered down Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 238 RCW bit is set or the Intent to Secure fuse value is set. See the Trust architecture overview section in the Secure Boot and Trust Architecture chapter for more information. Options: Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 239 1 FTM2_CH3 SDHC2_BASE_BASE field. NOTE: This field is ignored if SDHC2_BASE_BASE is not equal to 2'b00 SDHC2_EXT_CMD This field configures the Options: functionality of 0 GPIO1[24] Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 240 EC1_BASE field. 01 SAI4_TX_DATA, SAI4_TX_SYNC, SAI4_TX_BCLK 10 SAI4_RX_DATA, SAI4_RX_SYNC, SAI4_RX_BCLK 11 Reserved NOTE: This field is ignored if EC1_BASE is not equal to 2'b00 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 241 00 See SDHC2_EXT_* bit definition DATA[3:1] pins together with the SDHC2_EXT_* field. 01 SDHC2_DAT[3:1]. This option is only valid if SDHC2_BASE_BASE is configured for SDHC2 operation. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 242 CLK_OUT 00 GPIO1[31] pin. 01 CLK_OUT 10 RESET_REQ_B 11 Reserved NOTE: • RESET_REQ_B is selected through either RCW[382:383] or RCW[QSPI_IIC2]. Selection of Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 243 1.0. 426-428 Reserved. Must be set to all 0's. 429-430 USB1_DRVVBUS_BA This field configures the Options: functionality of the 00 GPIO2[0] USB1_DRVVBUS pin. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 244 1 MDC configured in open-drain mode 445-447 Reserved. Must be set to 000. PLL AND CLOCKING CONFIGURATION EXPANSION (BITS 448-511) 448-471 Reserved. Must be set to all 0's. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 245 DDR controllers after a valid RCW is restored. 4.4.5.3 RCW settings for hard-coded options Table 4-11. RCW settings for hard-coded RCW options RCW field cfg_rcw_src PLL CONFIGURATION (BITS 0-127) SYS_PLL_CFG 2'b00 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 246 2'b00 EC1_EXT_SAI4 2'b00 EC1_EXT_SAI2_TX 1'b0 EC1_EXT_SAI2_RX 1'b0 EC1_BASE 2'b00 (GPIO) UART1_BASE 2'b00 (GPIO) UART2_BASE_FLOW 2'b00 (GPIO) SDHC1_BASE 2'b00 (GPIO) SDHC2_BASE_DAT321 2'b00 (GPIO) SDHC2_BASE_BASE 2'b00 (GPIO) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 247 The following table provides the clocking configuration for both these modes: Table 4-12. POR configurations cfg_func_backup cfg_sysclk_sel Description External clock oscillator/generator-based clocking provides 25 MHz square wave input (on EXTAL) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 248 25 MHz input from Oscillator QuadSPI on-board crystal XTAL RCW[SerDes_INT_REFCLK] cfg_func_backup SerDes PLL1 cfg_sysclk_sel 125 MHz internal differential clock SD_REF_CLKn_P SerDes PLL2 100/125 MHz external differential clock SD_REF_CLKn_N Figure 4-3. Crystal based clocking mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 249 Depending on the system requirement, following guidelines must be followed while using the crystal or external clock oscillator/generator with different interfaces: • Crystal cannot be used as primary clock input for the chip when the following function(s) are enabled: • SATA QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 250 For the systems with RGMII PHY, either the crystal or clock oscillator/generator can be used. See the figure below for the RGMII PHY clocking with both crystal as well as clock oscillator/generator modes. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 251 Crystal or clock oscillator/generator must satisfy the clock tolerance of GTX_CLK required by the RGMII PHY. 4.4.6.2.3 SGMII use cases For the systems with SGMII PHY, an external clock oscillator/generator is required, as shown in the figure below: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 252 SGMII PHY clocking implementation in silicon revision 1.0. 4.4.6.2.4 SATA use cases For the systems with a SATA interface, an external clock oscillator/generator is required, as shown in the figure below: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 253 However, the interfaces can also be clocked by the external source (SD1_REF_CLK1). (See Valid reference clocks and PLL configurations for SerDes protocols for details regarding valid combinations of external reference clocks and RCW configurations.) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 254 25 MHz square wave from external clock oscillator/generator can be used on EXTAL and XTAL should be connected to GND. Figure 4-11. Clock subsystem block diagram - cluster group A QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 255 Note: Either a 25 MHz crystal is used with an on-chip crystal oscillator through pins (EXTAL/XTAL) or 25 MHz square wave from external clock oscillator/generator can be used on EXTAL and XTAL should be connected to GND. Figure 4-12. Clock subsystem block diagram - IP modules QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 256 The CLK_OUT signal can be configured to offer one of a variety of internal clock signals to external hardware for debug or diagnostic purposes. (See the clocking register (CLKPCSR) for details.) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 257 All I2C inerrupts are ORed together. I2C Bus Status Register (I2C_IBSR) for more information. 90-91 Reserved USB3 All USB 3.0 interrupts are ORed together and connected to this interrupt. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 258 Reserved SCFG_PFE PFE PCS status register 1 (PFEPCSSR1), interrupt enable control register (PFEINTENCR1), PFE PCS status register 2 (PFEPCSSR2), interrupt enable control register 2 (PFEINTENCR2), Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 259 PCI Express MSI implementation for more information. PEX1 PME Refer PM_PME messages in the Power Management chapter of PCI Express™ Base Specification, Revision 3.0 for more information. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 260 Internal RAM multi-bit ECC error Virtual CPU interface maintenance interrupt core 0 230-255 Reserved NOTE • There is no interrupt for MDIO. Software needs to use polling mechanism. • All reserved interrupts should be disabled. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 261 The Arm® Cortex®-A53 processor is an extremely power efficient Armv8 processor capable of supporting 32-bit and 64-bit code seamlessly. It makes use of a highly efficient 8-stage in-order pipeline balanced with advanced fetch and data access techniques for performance. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 262 • registers for managing interrupt sources, interrupt behavior, and interrupt routing to one or more processors • support for the following: • the Arm architecture security extensions • the Arm architecture virtualization extensions QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 263 OCRAM1 and OCRAM2. Also, the ECC error interrupt needs to be cleared in GIC (MBEE). Once completed, the host processor enables interrupt related to ECC errors from OCRAM1 and OCRAM2. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 264 On-Chip RAM memory controller (OCRAM) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 265 The OCRAM is 64KB of On-Chip SRAM, restricted to Secure World access only by the CSU. CSU related platform control registers are found in the Miscellaneous System Control Module. The MSCM provides error reporting related to attempted access control violations blocked by the CSU. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 266 QuadSPI (QSPI) memory space CSL4[8:0] 0_0011_0011 Reserved 0xBASE_0014 CSL5[24:16] 0_0011_0011 SATA controller registers CSL5[8:0] 0_0011_0011 USB 3.0 controllers registers 0xBASE_0018 CSL6[24:16] 0_0011_0011 Reserved CSL6[8:0] 0_0011_0011 Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 267 0_0011_0011 Reserved 0xBASE_005C CSL23[24:16] 0_0011_0011 C Controller 1 registers CSL23[8:0] 0_0011_0011 USB 2.0 controller registers 0xBASE_0060 CSL24[24:16] 0_0011_0011 Reserved CSL24[8:0] 0_0011_0011 C Controller 2 registers Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 268 CSL37[8:0] 0_0011_0011 Central Security Unit (CSU) registers 0xBASE_0098 CSL38[24:16] 0_0011_0011 Reserved CSL38[8:0] 0_0011_0011 SAI5 registers 0xBASE_009C CSL39[24:16] 0_0011_0011 Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 269 Lock bit corresponding to the slave. (It is written by secure software.) Not locked. Bits 16-23 can be written by software. Locked. Bits 16-23 cannot be written by software. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 270 Locked. Bits 0-7 cannot be written by software. Non-secured supervisor write access disabled Non-secured supervisor write access enabled Non-secured user write access disabled Non-secured user write access enabled Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 271 0xBASE_218 csu_sa0[11-10] Software-Override bit for DBGEN signal connectivity to core and debug components 0xBASE_218 csu_sa0[13-12] CP15SDISABLE for core 0 0xBASE_218 csu_sa0[15-14] Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 272 Secured access indicator SA15_n Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register. Stands for Non-Secured Access for that master. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 273 Secured access indicator SA9_n Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register. Stands for Non-Secured Access for that master. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 274 Secured access indicator SA3_n Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register. Stands for Non-Secured Access for that master. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 275 The on-chip RAM is implemented as a slave device on the 64-bit system AXI bus. There are two OCRAMs in the chip and access can be controlled through CSU peripheral register programming. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 276 Attempted writes to read-only registers are simply ignored (RO/WI). This section contains the target access fault information like CSLn attribute check logic plus an array of 128-bit register structures containing captured CSLn fault information. All the register accesses are privilege/supervisor QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 277 The CSLIER also contains a lock bit (RO) that may be set to disable writes to the register, preserving the enabled/disabled state of the CSLn interrupts. Address: 152_0000h base + C10h offset = 152_0C10h Reserv Lock Reserved Reset Reserved CIE8 Reserved CIE4 CIE2 CIE0 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 278 CIE4 = 0, the CSLn access check interrupt is disabled. if CIE4 = 1, the CSLn access check interrupt is enabled. The individual CIE4 are mapped to QuadSPI memory space. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 279 MSCM_CSF*R register. Additionally, the clearing of an interrupt flag in this register also clears the corresponding bit in the MSCM_CSLOVR register and rearms the logic for capturing the failed access information. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 280 The individual CIE12 are mapped to USB 3 Controller Register space(CCSR). This field is reserved. Reserved CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt. INT10 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 281 Stated differently, if a CSLn access check violation is detected and the corresponding MSCM_CSLIR[i] bit still asserted, the MSCM_CSOVR[i] bit is set. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 282 The individual CIE18 are mapped to OCRAM2 memory space. CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt. OVR17 if OVR17 = 0, the CSLn access check interrupt is disabled. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 283 OVR0 = 0, the CSLn access check interrupt is disabled. if OVR0 = 1, the CSLn access check interrupt is enabled. The individual CIE0 are mapped to PCI Express controller 1 IO config space and memory space. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 284 SATA Register space(CCSR) 0xDB0 Reserved 0xDC0 USB 3 controller Register space(CCSR) 0xDD0 - 0xE00 Reserved 0xE10 OCRAM1 Memory Space 0xE20 OCRAM2 Memory Space 0xE30 - 0xFFC Reserved All the register accesses are privilege/supervisor. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 285 152_0E18 0000_0000h (MSCM_CSFCR17) ACTZS CSLn Fail Status Master ID Register 7.3.2.12/ 152_0E1C 0000_0000h (MSCM_CSFIR17) ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/ 152_0E20 0000_0000h (MSCM_CSFAR18) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 286 The next sequential word at offset address 0xD04 + 16*n is reserved for systems where the address space is larger than 4 Gbytes. Address: 152_0000h base + D00h offset + (32d × i), where i=0d to 2d Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 287 FWT = 0, then the last captured CSLn access check violation was a read. if FWT = 1, then the last captured CSLn access check violation was a write. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 288 MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing of fail information is rearmed. Attempted privileged mode writes are ignored. Address: 152_0000h base + D0Ch offset + (32d × i), where i=0d to 2d Reserved FMID Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 289 Address: 152_0000h base + D80h offset + (32d × i), where i=0d to 1d Reset MSCM_CSFARn field descriptions Field Description 0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access check violation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 290 FNS = 0, the last captured CSLn access check violation was a secure access. if FNS = 1, the last captured CSLn access check violation was a nonsecure access. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 291 MSCM_CSFIRn field descriptions Field Description 0–26 This field is reserved. Reserved 27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access FMID check violation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 292 Address: 152_0000h base + DC0h offset + (16d × i), where i=0d to 0d Reset MSCM_CSFARn field descriptions Field Description 0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access check violation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 293 FNS = 0, the last captured CSLn access check violation was a secure access. if FNS = 1, the last captured CSLn access check violation was a nonsecure access. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 294 MSCM_CSFIRn field descriptions Field Description 0–26 This field is reserved. Reserved 27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access FMID check violation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 295 Address: 152_0000h base + E10h offset + (16d × i), where i=0d to 1d Reset MSCM_CSFARn field descriptions Field Description 0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access check violation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 296 FNS = 0, the last captured CSLn access check violation was a secure access. if FNS = 1, the last captured CSLn access check violation was a nonsecure access. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 297 MSCM_CSFIRn field descriptions Field Description 0–26 This field is reserved. Reserved 27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access FMID check violation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 298 Miscellaneous System Control Module (MSCM) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 299 8.2 Secure system counter register descriptions The secure system counter memory map provides register list for the secure world to access the counter values. 8.2.1 Secure_System_counter Memory map system_counter base address: 2B0_0000h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 300 Counter frequency mode table base frequency register (CNTFID0) description. 8.2.2 Control register (CNTCR) 8.2.2.1 Offset Register Offset CNTCR 8.2.2.2 Function This register enables the counter. 8.2.2.3 Diagram Bits Reserved Reset Bits Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 301 This register indicates the current LSB count value of the 64-bit counter. The register is writable only by secure writes. When the counter is enabled, the effect of writing the register is unpredictable. 8.2.3.3 Diagram Bits CNCTV1 Reset Bits CNCTV1 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 302: Offset
This register indicates the current MSB count value of the 64-bit counter. The register is writable only by secure writes. When the counter is enabled, the effect of writing the register is unpredictable. 8.2.4.3 Diagram Bits CNCTV2 Reset Bits CNCTV2 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 303: Fields
SYSCLK_FREQ/4 frequency clock. The initial value of this register is 25 MHz (100 MHz/4). Software needs to update this register initially to reflect the correct frequency based on system clock frequency. 8.2.5.3 Diagram Bits CNT_BASE Reset Bits CNT_BASE Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 304: Fields
MSB of counter count value register (CNCTV2_RO2) 0000_0000h 8.3.2 LSB of Counter Count Value (CNCTV_RO1) 8.3.2.1 Offset Register Offset CNCTV_RO1 8.3.2.2 Function This register is read-only and contains the current LSB count value of the 64-bit counter. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 305 CNCTV_RO1 8.3.3 MSB of counter count value register (CNCTV2_RO2) 8.3.3.1 Offset Register Offset CNCTV2_RO2 8.3.3.2 Function The register is read-only and contains the current MSB count value of the 64-bit counter. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 306 Non-secure system counter register descriptions 8.3.3.3 Diagram Bits CNCTV_RO2 Reset Bits CNCTV_RO2 Reset 8.3.3.4 Fields Field Function 0-31 Counter count value bits CNCTV[63:32] CNCTV_RO2 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 307 CCI-400 level, as the system beyond CCI-400 does not support the "lock transactions". Transaction should be marked with domain setting, such as "01- Inner sharable" or "10- Outersharable". CCI-400 includes the following connections: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 308 • M1: ACE-Lite master interface (DDR controller) • M2: Unused core cluster controller CCI-400 OCRAM1 Not Used OCRAM2 QuadSPI eSDHC1 eSDHC2 USB 2.0 Not Used USB 3.0 PEX1 SATA 3.0 Figure 9-1. Chip interconnect QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 309 CCI base address: 118_0000h Offset Register Width Access Reset value (In bits) Control Override Register (Control_Override_Register) description. Speculation Control Register (Speculation_Control_Register) description. Secure Access Register (Secure_Access_Register) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 310 Snoop Control Registers (Snoop_Control_Register_S2) description. 3004h Shareable Override Registers (Shareable_Override_Register_S2) description. 3100h Read Channel QoS Value Override Register (Read_Qos_Override_ Register_S2) description. 3104h Write Qos Override Register (Write_Qos_Override_Register_S2) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 311 Max OT Registers (Max_OT_Register_S4) description. 5130h Regulator Target Registers (Target_Latency_Register_S4) description. 5138h QoS Range Register (Qos_Range_Register_S4) description. 5268h QoS Regulator Scale Factor Registers (Latency_Regulation_Regis ter_S3) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 312 Secure OS. You can access the Control Override Register using Secure transactions only, irrespective of the programming of the Secure Access Register . Available in all CCI-400 configurations. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 313 1b - Disable speculative fetches from all master interfaces. DVM Message Disable 0b - Send DVM messages according to the Snoop Control Registers. See Snoop Control Registers. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 314 Speculative fetches are not issued if they are disabled in either the slave or master interface for a particular transaction. Access controlled by Secure Access Register, see Secure Access Register. Available in all CCI-400 configurations. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 315 Disable speculative fetches for transactions through a slave interface. One bit for each slave interface: ative_Fetches_S S4, S3, S2, S1, and S0: 00000b - Enable speculative fetches. 00001b - Disable speculative fetches. 15-3 Reserved — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 316 The Secure Access register controls secure access. You can only write to this register using Secure transactions. Available in all CCI-400 configurations. NOTE This register enables Non-secure access to the CCI-400 registers for all masters. This compromises the security of your system. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 317: Ch Status Register (Status_Register)
Secure_Access Non-secure register access override: _Control 0b - Disable Non-secure access to CCI-400 registers. 1b - Enable Non-secure access to CCI-400 registers. 9.2.5 Status Register (Status_Register) 9.2.5.1 Offset Register Offset Status_Register QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 318 Field Function 31-1 Reserved — CCI_Status CCI_Status Indicates whether any changes to the snoop or DVM enables is pending in the CCI-400 0b - No change pending. 1b - Change pending. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 319: Imprecise Error Register (Imprecise_Error_Register)
There are no usage constraints. Available in all CCI-400 configurations. NOTE If any of the imprecise error indicator bits are set, the nERRORIRQ signal is asserted, active LOW. 9.2.6.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 320 1b - An error response has been received, but not signalled precisely. 9.2.7 Snoop Control Registers (Snoop_Control_Register_S0 - Snoop_Control_Register_S4) 9.2.7.1 Offset For a = 0 to 4: Register Offset Snoop_Control_Register 1000h + (a × 1000h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 321 • If DVM messages are disabled in the Control Override Register, write accesses to the DVM enable bit[1] are ignored. 9.2.7.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 322 1004h + (a × 1000h) ister_Sa 9.2.8.2 Function The Shareable Override register overrides shareability of normal transactions through this interface. The following transaction types are unaffected by any override: • FIXED-type bursts. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 323 An exclusive write then receives an OKAY response to indicate that the slave does not support exclusive accesses. 9.2.8.3 Diagram Bits Reserved Reset Bits Reset 9.2.8.4 Fields Field Function 31-2 Reserved — AxDOMAIN override QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 324 Accessible using only Secure accesses, unless you set the Secure Access Register. See Secure Access Register bit assignments. Available in all CCI-400 configurations. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 325 Reads what value is currently applied to transactions with ARQOS=0, provided QOSOVERRIDE is HIGH e_readback and the QoS value regulator is enabled. Reserved — ARQOS value ARQOS_value ARQOS value override for slave interface 9.2.10 Write Qos Override Register (Write_Qos_Override_Regis ter_S0 - Write_Qos_Override_Register_S4) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 326 Accessible using only Secure accesses, unless you set the Secure Access Register. See Secure Access Register bit assignments. Available in all CCI-400 configurations. 9.2.10.3 Diagram Bits Reserved Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 327 Secure Access Register bit assignments on page 3-10. Available in all CCI-400 configurations. NOTE When outstanding transaction regulation is enabled or disabled for an interface, changes take effect only when there are no outstanding transactions in that interface. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 328 1b - Quiesce High mode. The QoS value tends to the maximum when the master is idle. ARQOS regulation mode Configures the mode of the QoS value regulator for read transactions: Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 329 Enable QoS value regulation on writes for slave interfaces ion_write 9.2.12 Max OT Registers (Max_OT_Register_S0 - Max_OT_Regis ter_S4) 9.2.12.1 Offset For a = 0 to 4: Register Offset Max_OT_Register_Sa 1110h + (a × 1000h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 330 Secure accesses, unless you set the Secure Access Register. See Secure Access Register bit assignments. Available in all CCI-400 configurations. 9.2.12.3 Diagram Bits Reset Bits Reset 9.2.12.4 Fields Field Function 31-30 Reserved — 29-24 Int_OT_AR Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 331 One register exists for each slave interface. Accessible using only Secure accesses, unless you set the Secure Access Register. See Secure Access Register bit assignments. Only has an effect when QOSOVERRIDE is HIGH for the associated interface. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 332 — 11-0 AW channel target latency AW_Lat 9.2.14 QoS Range Register (Qos_Range_Register_S0 - Qos_ Range_Register_S4) 9.2.14.1 Offset For a = 0 to 4: Register Offset Qos_Range_Register_Sa 1138h + (a × 1000h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 333 31-28 Reserved — 27-24 Maximum ARQOS value Max_ARQOS 23-20 Reserved — 19-16 Minimum ARQOS value Min_ARQOS 15-12 Reserved — 11-8 Maximum AWQOS value Max_AWQOS Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 334 Table 9-2. Mapping of Scale Factor Register value to Regulator scale factor Scale Factor Register value Scale factor –5 –6 –7 –8 –9 –10 –11 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 335 AWQOS Scale Factor –5 –12 AW_Scale_Fact AWQOS scale factor, power of 2 in the range 2 9.3 Functional Description This chapter describes the functionality of the CoreLink CCI-400 Cache Coherent Interconnect. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 336: Snoop Control Registers (Snoop_Control_Register_S0)
These bits are only sampled at reset. • There are bits in the Control Override Register to disable all snooping or all DVM message broadcast, irrespective of the programming of the Snoop Control Register. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 337 You can use the PMU to record the number of retry transactions for each master interface. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 338 • Non-secure read requests to Secure registers receive a DECERR response, RRESP[1:0] == 0b11 , and zeroed data. • Non-secure write requests to Secure registers receive a DECERR response, BRESP[1:0] == 0b11 and are Write-Ignored (WI). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 339 (See Table "Interrupt Assignments" in the "Interrupt Assignments" chapter). You can identify the interface that received the error response by reading the Imprecise Error Register. See Imprecise Error Register (Impr ecise_Error_Register). 9.3.5.1 Imprecise errors QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 340 The CCI-400 supports all types of AMBA 4 barrier transactions. Each slave interface broadcasts these to every master interface, ensuring that intermediate transaction source and sink points observe the barrier correctly. NOTE Only MMDC supports barrier transactions in the chip. 9.3.7 DVM messages QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 341 • No other bus master except A53 supprots DVM messaging in the chip. 9.3.8 Quality of Service The CCI-400 supports QoS with the following independent mechanisms: • QoS value • Regulation based on outstanding transactions 9.3.8.1 QoS value QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 342 QoS value, up to the programmed maximum, under worst case conditions. The maximum value for each regulator is 0 at reset, so you must program a maximum value before the regulator can be used. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 343: Register_S0)
ARQOS and AWQOS values are driven by those generated by the regulators, if the original transaction has a zero QoS value and the QOSOVERRIDE configuration input is HIGH. You can program the regulator mode using the QoS Control Registers. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 344 50 cycles, then a master can issue a transaction. It finishes after 50 cycles and it cannot issue the next transaction until 100 cycles, maintaining a mean number of outstanding transactions as 0.5. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 345 • The maximum number of slots available for medium priority requests is 32 - 1 = 31. • The maximum number of slots available for low priority requests is 32 - 3 - 1 = 28. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 346: Max Ot Registers (Max_Ot_Register_S0)
• Read Channel QoS Value Override Register. • Write Channel QoS Value Override Register. • QoS Control Register. • Max OT Registers. • Regulator Target Registers. • QoS Regulator Scale Factor Registers. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 347 The software should configure the TZASC bypass mux (csu_sa1[2-3]) to disable the bypass operation and use the TZASC default region before any transaction goes to DDR. The figure below shows the TZASC in an example system: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 348 • tzasc_int. The assertion of this signals is controlled by the TZASC interrupt (#125). Refer Internal interrupt sources for details. The figure below shows the signals provided by the TZASC: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 349 • Fail status : These registers provide information about an access that failed because of insufficient permissions. • Control : Use these registers to enable the TZASC to perform security inversion or speculative accesses. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 350 Region Setup Low 4 Register (region_setup_low_4) 0000_0000h 144h Region Setup High 4 Register (region_setup_high_4) 0000_0000h 148h Region Attributes 4 Register (region_attributes_4) 0000_001Ch 150h Region Setup Low 5 Register (region_setup_low_5) 0000_0000h Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 351 Region Setup High 15 Register (region_setup_high_15) 0000_0000h 1F8h Region Attributes 15 Register (region_attributes_15) 0000_001Ch E00h Integration Test Control Register (itcrg) 0000_0000h E04h Integration Test Input Register (itip) 0000_0000h E08h Integration Test Output Register (itop) 0000_0000h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 352 Reset 10.3.2.4 Fields Field Function 31-14 Reserved, Should be Zero (SBZ). — 13-8 address_width address_width Returns the width of the AXI address bus. Read as: Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 353 Register Offset action 10.3.3.2 Function The action Register controls the response signaling behavior of the TZASC to region permission failures. There are no usage constraints.Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 354 = sets tzasc_int LOW and issues a DECERR response b10 = sets tzasc_int HIGH and issues an OKAY response b11 = sets tzasc_int HIGH and issues a DECERR response. 10.3.4 Lockdown Range Register (lockdown_range) 10.3.4.1 Offset Register Offset lockdown_range QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 355 = region no_of_regions–1 to region no_of_regions–2 are locked b0010 = region no_of_regions–1 to region no_of_regions–3 are locked b0011 = region no_of_regions–1 to region no_of_regions–4 are locked b1111 = region no_of_regions–1 to region no_of_regions–16 are locked. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 356 LOW. When secure_boot_lock is HIGH for one aclk period, or more then the TZASC ignores writes to this register. This register is available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 357 Modifies the access type of the lockdown_range Register: 0 = no effect. lockdown_range Register remains RW. 1 = lockdown_range Register is RO. See Lockdown Range Register for more information. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 358 Reserved, Should be Zero (SBZ). — overrun overrun When set to 1, it indicates the occurrence of two or more region permission failures since the interrupt was last cleared Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 359 Register Offset int_clear 10.3.7.2 Function The int_clear Register clears the interrupt. There are no usage constraints. Available in all configurations of the TZASC. 10.3.7.3 Diagram Bits int_clear Reset Bits int_clear Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 360 The fail_address_low Register returns the address, the lower 32-bits, of the first access that failed a region permission, after the interrupt was cleared. There are no usage constraints. Available in all configurations of the TZASC. 10.3.8.3 Diagram Bits add_status_low Reset Bits add_status_low Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 361 There are no usage constraints. Only available when the TZASC has an AXI address width of greater than 32 bits. 10.3.9.3 Diagram Bits add_status_high Reset Bits add_status_high Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 362 The fail_control Register returns the control status information of the first access that failed a region permission, after the interrupt was cleared. There are no usage constraints. Available in all configurations of the TZASC. 10.3.10.3 Diagram Bits Reset Bits Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 363 After clearing the interrupt status, this bit indicates whether the first access to fail a region permission check was privileged. Read as: 0 = unprivileged access 1 = privileged access. 19-0 Reserved, Should be Zero (SBZ). — 10.3.11 Fail ID Register (fail_id) 10.3.11.1 Offset Register Offset fail_id QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 364 Returns the master AXI ID of the first access to fail a region permission check after the interrupt was cleared. The size of this bit field is [n:0] where n = AID_WIDTH-1. 10.3.12 Speculation Control Register (speculation_control) 10.3.12.1 Offset Register Offset speculation_control QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 365 1 = write access speculation is disabled. read_speculation read_speculatio Controls the read access speculation: 0 = read access speculation is enabled. This is the default. 1 = read access speculation is disabled. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 366 Usage constraints The lockdown_select Register can restrict the access type of this register to RO. See Lockdown Select Register for more details. Available in all configurations of the TZASC. 10.3.13.3 Diagram Bits Reserved Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 367 1 = security inversion is permitted. This enables a region to be accessible to masters in Non-secure state but not accessible to masters in Secure state. 10.3.14 Region Setup Low 0 Register (region_setup_low_0) 10.3.14.1 Offset Register Offset region_setup_low_0 100h 10.3.14.2 Diagram Bits base_address_low0 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 368 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 369 10.3.16 Region Attributes 0 Register (region_attributes_0) 10.3.16.1 Offset Register Offset region_attributes_0 108h 10.3.16.2 Function The region_attributes_0 register controls the permissions for region 0. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 370 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field controls whether the TZASC permits the transaction to proceed. 27-0 Reserved, Should be Zero (SBZ). — 10.3.17 Region Setup Low 1 Register (region_setup_low_1) 10.3.17.1 Offset Register Offset region_setup_low_1 110h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 371 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 372 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 373 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 374 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 375 Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size1 size1 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 376 0 = region n is disabled 1 = region n is enabled. 10.3.20 Region Setup Low 2 Register (region_setup_low_2) 10.3.20.1 Offset Register Offset region_setup_low_2 120h 10.3.20.2 Diagram Bits base_address_low2 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 377 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 378 Register Offset region_attributes_2 128h 10.3.22.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 379 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 380 See Table 313 on page 318 and Table 314 on page 319. 10.3.22.3 Diagram Bits Reserved Reset Bits Reset 10.3.22.4 Fields Field Function 31-28 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 381 TZASC applies to the base address to ensure that a region starts on the boundary of the region size. Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.23 Region Setup Low 3 Register (region_setup_low_3) 10.3.23.1 Offset Register Offset region_setup_low_3 130h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 382 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 383 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 384 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 385 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 386 Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size3 size3 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 387 0 = region n is disabled 1 = region n is enabled. 10.3.26 Region Setup Low 4 Register (region_setup_low_4) 10.3.26.1 Offset Register Offset region_setup_low_4 140h 10.3.26.2 Diagram Bits base_address_low4 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 388 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 389 Register Offset region_attributes_4 148h 10.3.28.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 390 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 391 See Table 313 on page 318 and Table 314 on page 319. 10.3.28.3 Diagram Bits Reserved Reset Bits Reset 10.3.28.4 Fields Field Function 31-28 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 392 TZASC applies to the base address to ensure that a region starts on the boundary of the region size. Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.29 Region Setup Low 5 Register (region_setup_low_5) 10.3.29.1 Offset Register Offset region_setup_low_5 150h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 393 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 394 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 395 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 396 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 397 Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size5 size5 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 398 0 = region n is disabled 1 = region n is enabled. 10.3.32 Region Setup Low 6 Register (region_setup_low_6) 10.3.32.1 Offset Register Offset region_setup_low_6 160h 10.3.32.2 Diagram Bits base_address_low6 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 399 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 400 Register Offset region_attributes_6 168h 10.3.34.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 401 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 402 See Table 313 on page 318 and Table 314 on page 319. 10.3.34.3 Diagram Bits Reserved Reset Bits Reset 10.3.34.4 Fields Field Function 31-28 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 403 TZASC applies to the base address to ensure that a region starts on the boundary of the region size. Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.35 Region Setup Low 7 Register (region_setup_low_7) 10.3.35.1 Offset Register Offset region_setup_low_7 170h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 404 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 405 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 406 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 407 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 408 Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size7 size7 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 409 0 = region n is disabled 1 = region n is enabled. 10.3.38 Region Setup Low 8 Register (region_setup_low_8) 10.3.38.1 Offset Register Offset region_setup_low_8 180h 10.3.38.2 Diagram Bits base_address_low8 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 410 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 411 Register Offset region_attributes_8 188h 10.3.40.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 412 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 413 See Table 313 on page 318 and Table 314 on page 319. 10.3.40.3 Diagram Bits Reserved Reset Bits Reset 10.3.40.4 Fields Field Function 31-28 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 414 TZASC applies to the base address to ensure that a region starts on the boundary of the region size. Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.41 Region Setup Low 9 Register (region_setup_low_9) 10.3.41.1 Offset Register Offset region_setup_low_9 190h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 415 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 416 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 417 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 418 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 419: Diagram
Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size9 size9 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 420: Offset
0 = region n is disabled 1 = region n is enabled. 10.3.44 Region Setup Low 10 Register (region_setup_low_10) 10.3.44.1 Offset Register Offset region_setup_low_10 1A0h 10.3.44.2 Diagram Bits base_address_low10 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 421 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 422 Register Offset region_attributes_10 1A8h 10.3.46.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 423 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 424 See Table 313 on page 318 and Table 314 on page 319. 10.3.46.3 Diagram Bits sp10 Reserved Reset Bits Reset 10.3.46.4 Fields Field Function 31-28 sp10 sp10 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 425 Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.47 Region Setup Low 11 Register (region_setup_low_11) 10.3.47.1 Offset Register Offset region_setup_low_11 1B0h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 426 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 427 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 428 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 429 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 430 Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size11 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 431 0 = region n is disabled 1 = region n is enabled. 10.3.50 Region Setup Low 12 Register (region_setup_low_12) 10.3.50.1 Offset Register Offset region_setup_low_12 1C0h 10.3.50.2 Diagram Bits base_address_low12 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 432 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 433 Register Offset region_attributes_12 1C8h 10.3.52.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 434 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 435 See Table 313 on page 318 and Table 314 on page 319. 10.3.52.3 Diagram Bits sp12 Reserved Reset Bits Reset 10.3.52.4 Fields Field Function 31-28 sp12 sp12 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 436 Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.53 Region Setup Low 13 Register (region_setup_low_13) 10.3.53.1 Offset Register Offset region_setup_low_13 1D0h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 437 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 438 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 439 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 440 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 441: Diagram
Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size13 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 442: Offset
0 = region n is disabled 1 = region n is enabled. 10.3.56 Region Setup Low 14 Register (region_setup_low_14) 10.3.56.1 Offset Register Offset region_setup_low_14 1E0h 10.3.56.2 Diagram Bits base_address_low14 Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 443 The region_setup_high register is none for region 0, for other regions it controls the base address [63:32] of region n.There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 444 Register Offset region_attributes_14 1E8h 10.3.58.2 Function The region_attributes_n register controls the permissions, region size, subregion disable, and region enable. There are no usage constraints. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 445 512TB Bits [48:15] must be zero b110001 Bits [49:15] must be zero b110010 Bits [50:15] must be zero b110011 Bits [51:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 446 See Table 313 on page 318 and Table 314 on page 319. 10.3.58.3 Diagram Bits sp14 Reserved Reset Bits Reset 10.3.58.4 Fields Field Function 31-28 sp14 sp14 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 447 Enable for region n: 0 = region n is disabled 1 = region n is enabled. 10.3.59 Region Setup Low 15 Register (region_setup_low_15) 10.3.59.1 Offset Register Offset region_setup_low_15 1F0h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 448 If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain bits depending on the region size. See Table on register size for more information. 14-0 Reserved, Should be Zero (SBZ). — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 449 The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 450 Bits [32:15] must be zero b100001 16GB Bits [33:15] must be zero b100010 32GB Bits [34:15] must be zero b100011 64GB Bits [35:15] must be zero Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 451 Bits [62:15] must be zero b111111 16EB Bits [63:15] must be zero [1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the base address. See Table 313 on page 318 and Table 314 on page 319. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 452 Bit [10] = 1 Subregion 2 is disabled. Bit [9] = 1 Subregion 1 is disabled. Bit [8] = 1 Subregion 0 is disabled. Reserved, Should be Zero (SBZ). — size15 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 453 E00h 10.3.62.2 Function The itcrg register enables the integration test logic. Use this in integration test mode. Available in all configurations of the TZASC. 10.3.62.3 Diagram Bits Reserved Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 454 The itip register enables a processor to read the status of secure_boot_lock. Integration test logic must be enabled otherwise reads return 0x0. See Integration Test Control Register for information about enabling the integration test logic. Available in all configurations of the TZASC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 455 Chapter 10 Arm CoreLink™ TrustZone Address Space Controller TZC-380 10.3.63.3 Diagram Bits Reserved Reset Bits Reset 10.3.63.4 Fields Field Function 31-1 Reserved. — itip_secure_boot_lock itip_secure_boot _lock 10.3.64 Integration Test Output Register (itop) 10.3.64.1 Offset Register Offset itop E08h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 456 0 = tzasc_int is LOW 1 = tzasc_int is HIGH. 10.4 Functional description This chapter describes the TZASC operation. It contains the following sections: • Functional operation • Constraints of use QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 457 • Region enable. • Security permissions. • Base address. • Size. The minimum address size of a region is 32KB. • Subregion disable. See Subregions. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 458 10.4.1.3 Subregions The TZASC divides each region into eight equal-sized, non-overlapping subregions. Figure 10-5 shows the subregions for an example region that is programmed to occupy an address span of 32KB. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 459 • region 0 is overlapped with all regions. With some subregions of region 1, region 2, and region 3 are disabled, and the resulting region permissions of the entire address space is shown in the Figure 10-6. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 460 A region is assigned a security permissions field, sp<n>, in its region_attributes_<n> Register that enables you to have complete control of the permissions for that region. See Register Descriptions. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 461 1. See Region Attributes 0 Register (region_attributes_0) for programming information. Programming security permissions when security inversion is enabled QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 462 Region size Description address Region_0 Enable 1100 Secure Read (Default) Write access (RW). Region_1 Enable 64MB b011001 1111 Non-secure Read or Write access (R/W), Secure R/W. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 463 RO for streaming from the normal world to the secure world. Region_7 Enable 0x3C80000 512KB b010010 1110 Non-secure RO, Secure RW for streaming from the Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 464 NA for FLASH holding normal world OS plus disk. Region_13 Enable 0xF0000000 b010011 1100 Non-secure NA, Secure RW for FLASH for secure boot, secure world Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 465 NOTE The action Register controls whether the TZASC signals to the master when a region permission failure occurs, and if so, the type of response it provides. See Action register (action). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 466 Speculation Control Register (speculation_cont rol). • security_inversion_en Register. See Security Inversion Register (security_inversion_ en). • lockdown_range Register. See Lockdown Range Register (lockdown_range). Locking down the region using lockdown_range and lockdown_select registers QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 467 Secure state and Non-secure state, the TZASC might deny a transaction and therefore the slave would not receive the latter part of the locked transaction sequence. Reads and writes QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 468 Normal world and Secure world use. NOTE There is no direct mechanism to ascertain if there are any outstanding AXI transactions, and so the designer must use their system knowledge to apply reasonable mechanisms. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 469 Chapter 10 Arm CoreLink™ TrustZone Address Space Controller TZC-380 It is recommended that any DECERR, or TZASC interrupt handler is designed to expect, and potentially ignore events generated under these circumstances. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 470 Functional description QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 471 USB3 parameter 2 control register (USB3PRM2CR) 17C1_FF48h USB3 parameter 3 control register (USB3PRM3CR) 0019_0000h 130h Core0 soft reset register (CORE0_SFT_RST) 0000_0000h 154h FTM chain configuration register (FTM_CHAIN_CONFIG) 0000_0000h Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 472 680h Core boot control register (COREBCR) FFFF_FFFFh 2000h Shared message signaled interrupt index register (PEX1MSIIR) 0000_0000h 2004h Shared message signaled interrupt register (PEX1MSIR) 0000_0000h 11.2.2 USB3 parameter 1 control register (USB3PRM1CR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 473 It drives the value of USB3 COMPDISTUNE signal. COMPDISTUNE Disconnect threshold adjustment: It adjusts the voltage level for the threshold used to detect a disconnect event at the host. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 474 It drives the value of USB3 TXVREFTUNE signal. TXVREFTUNE HS DC voltage level adjustment: It adjusts the high speed DC level voltage. 26-31 It drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal. PCSTXDEEMP H3P5DB QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 475 LFPS in U3 and U2 states. It masks the incoming LFPS for the number of reference clock cycles equal to the value of pcs_rx_los_mask_val[9:0]. This control filters out short, non-compliant LFPS glitches sent by a non-compliant host. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 476 Tx voltage boost level: It sets the boosted transmit launch amplitude (mVppd). 29-31 Reserved — 11.2.4 USB3 parameter 3 control register (USB3PRM3CR) 11.2.4.1 Offset Register Offset USB3PRM3CR 11.2.4.2 Function USB3PRM3CR contains the USB3 parameters signals. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 477 LOS is bypassed and based on the tx0_en input so that rx0_los = !tx0_data_en. 9-15 It drives the value of USB3 mpll_multiplier signal. MPLL_MULT MPLL frequency multiplier control: It multiplies the reference clock to a frequency suitable for intended operating speed. 16-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 478 Bits Reserved Reset 11.2.5.4 Fields Field Function Core 0 soft reset request. This bit is self clearing. SOFT_RESET 0b - default 1b - Soft reset core 0 1-31 Reserved — Reserved QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 479 Reset 11.2.6.4 Fields Field Function 0-13 Reserved — Reserved FTM2 chaining FTM_CHN2 0b - FTM2 is not chained 1b - FTM2 is chained FTM1 chaining Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 480 32 MB. 11.2.7.3 Diagram Bits ALTCBAR Reset Bits ALTCBAR Reserved Reset 11.2.7.4 Fields Field Function 0-23 Alternate configuration base address register for PBL Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 481 This register contains bits for selecting the clock source for QuadSPI and enabling or disabling the QuadSPI clock. It also provides bits for using different ratios of core PLL to drive the QuadSPI clock. 11.2.8.3 Diagram Bits CLK_SEL Reserved Reserved Reset Bits Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 482: Fields
This register contains bits for write port QoS inputs to CCI-400. Note that the bits are described as [x:x+3]; but these are connected to QoS ports as [3:0]. So, there is a bit reversal involved. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 483 QoS[3:0] for PFE HDBUD master interface PFE2_QOS 12-15 Reserved — 16-19 Reserved — 20-23 QoS[3:0] for PEX1 PEX1_QOS 24-27 QoS[3:0] for SEC SEC_QOS 28-31 Reserved — 11.2.10 WR QoS2 register (WR_QoS2) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 484 11.2.10.4 Fields Field Function QoS[3:0] for USB3 USB3_QOS 4-11 Reserved — 12-15 QoS[3:0] for A53 A53_QOS 16-19 QoS[3:0] for eSDHC2 ESDHC2_QOS 20-23 QoS[3:0] for eSDHC1 ESDHC1_QOS Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 485 [x:x+3]; but these are connected to QoS ports as [3:0]. So, there is a bit reversal involved. 11.2.11.3 Diagram Bits Reserved PFE1_QOS PFE2_QOS Reserved Reset Bits Reserved PEX1_QOS SEC_QOS Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 486 This register contains bits for read port QoS inputs to CCI-400. Note that the bits are described as [x:x+3]; but these are connected to QoS ports as [3:0]. So, there is a bit reversal involved. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 487: Diagram
QoS[3:0] for eSDHC2 ESDHC2_QOS 20-23 QoS[3:0] for eSDHC1 ESDHC1_QOS 24-27 QoS[3:0] for USB2 USB2_QOS 28-31 QoS[3:0] for SATA SATA_QOS 11.2.13 Snoop configuration control register (SNPCNFGCR) 11.2.13.1 Offset Register Offset SNPCNFGCR 1A4h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 488 Drives USB3 read snoop signal USBRDSNP Drives USB3 write snoop signal USBWRSNP Drives Debug read snoop signal DBGRDSNP Drives Debug write snoop signal DBGWRSNP Drives eDMA snoop signal Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 489 This register contains the bit to enable the soft reset functionality. 11.2.14.3 Diagram Bits Reset Bits Reserved Reset 11.2.14.4 Fields Field Function Enable/disable the core soft reset functionality Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 490 If not configured, its reset value will be 0x0 and the first instruction will be executed from the internal boot ROM. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 491 11.2.16 Core reset vector base address register 0 (RVBAR0_1) 11.2.16.1 Offset Register Offset RVBAR0_1 224h 11.2.16.2 Function This register controls the reset vector base address for core for bits [33:2]. This register should be programmed in the PBI phase. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 492 11.2.16.3 Diagram Bits RVBAR0_1 Reset Bits RVBAR0_1 Reset 11.2.16.4 Fields Field Function 0-31 Core reset vector base address for bits [39:34]. RVBAR0_1 11.2.17 Core low power mode control status register (LPMCSR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 493 Status bit for SMPEN signal of core 0. SMPEN0 Status bit for CPUQDENY signal for core 0. CPUQDENY0 Status bit for CPUQACCEPTn signal for core 0. CPUQACCEPT Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 494 11.2.18 SDHC IO VSEL control register (SDHCIOVSELCR) 11.2.18.1 Offset Register Offset SDHCIOVSELCR 408h 11.2.18.2 Function This register contains bits to support SDHC IO voltage switching. 11.2.18.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 495 1b - Change the SD bus supply voltage to low voltage range (1.8V) 11.2.19 USB powerfault select register (USB_PWRFAULT_SEL 11.2.19.1 Offset Register Offset USB_PWRFAULT_SEL 414h 11.2.19.2 Function This register defines the sampling of USB1_PWRFAULT by the USB1 controller. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 496 1b - PWRFAULT pin is shared between the USB 3.0 and USB 2.0 interfaces. 11.2.20 USBPHY control register (USB_PHY_CTRL) 11.2.20.1 Offset Register Offset USB_PHY_CTRL 418h 11.2.20.2 Function This register contains control bits for USBPHY. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 497 26 -- fsel bit 3 bit 27 -- fsel bit 2 bit 28 -- fsel bit 1 bit 29 -- fsel bit 0 30-31 Reserved — 11.2.21 Cluster PM control register (CLUSTERPMCR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 498 Reset 11.2.21.4 Fields Field Function 0-30 Reserved — WFIL2 enable 0b - No action (default) WFIL2EN 1b - STANDBYWFIL2 gets asserted when the core executes STANBYWFI 11.2.22 Pinmux control register (PMUXCR0) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 499 Software override for QuadSPI multiplexing. QSPI_MUX_OV 0b - Override disabled (default) 1b - Override enabled Software configures alternate functionality of the QuadSPI pins for 1-bit interface. 0b - QSPI_A_DAT0/QSPI_A_SCK/QSPI_A_CS0 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 500 10b - QSPI_A_DATA2, QSPI_A_DATA3 11b - Reserved 6-31 Reserved — 11.2.23 RGMII port control register (RGMIIPCR) 11.2.23.1 Offset Register Offset RGMIIPCR 434h 11.2.23.2 Function This register contains control bits of the RGMII ports. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 501 0b - Reserved SETFD 1b - Forces full duplex RGMII mode (This bit is valid only if EN_AUTO =0) 11.2.24 RGMII port status register (RGMIIPSR) 11.2.24.1 Offset Register Offset RGMIIPSR 43Ch QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 502 0b - No link is established or RGMII PHY does not support the optional in-band signaling RGFD 1b - RGMII full duplex link is established. This bit is valid if PHY supports the optional in-band signaling. 4-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 503 This register contains bits to log the PCS layer events for MAC1 of PFE in the SGMII mode. 11.2.25.3 Diagram Bits Reserved Reset Bits Reserved Reset 11.2.25.4 Fields Field Function Link synchronization event Auto negotiation status New page received by auto negotiation function 3-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 504 Interrupt enable bit for link synchronization event on PFE MAC1. PCS_EN Interrupt enable bit for auto negotiation on PFE MAC1. AN_EN Interrupt enable bit for new page received on auto negotiation on PFE MAC1. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 505 This register contains bits to log the PCS layer events for MAC2 of PFE in the SGMII mode. 11.2.27.3 Diagram Bits Reserved Reset Bits Reserved Reset 11.2.27.4 Fields Field Function Link synchronization event Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 506 11.2.28.1 Offset Register Offset PFEINTENCR2 44Ch 11.2.28.2 Function This register contains control bits to generate an interrupt (IRQ[154]) from PCS layer events of PFE MAC2. 11.2.28.3 Diagram Bits Reset Bits Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 507 11.2.29 PFE error control register (PFEERRCR) 11.2.29.1 Offset Register Offset PFEERRCR 450h 11.2.29.2 Function This register contains control bits for the error response received by PFE for read and write requests if enabled by PFEINTENCR. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 508 Read error response is captured for PFE HDBUS msster Interface. Write 1 to clear. RDERSPP2 4-31 Reserved — 11.2.30 PFE error interrupt enable control register (PFEERRIN TENCR) 11.2.30.1 Offset Register Offset PFEERRINTENCR 454h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 509 Interrupt enable bit for write error response captured for PFE HDBUS master interface. WRERSPENP2 Interrupt enable bit for read error response captured for PFE HDBUS master Interface. RDERSPENP2 4-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 510 0b - Non bufferable (default) 1b - Bufferable Control bit for AWCACHE[0] attribute. AWCACHE0 0b - Non bufferable (default) 1b - Bufferable Control bit for ARCACHE[1] attribute. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 511 — 11.2.32 PFEB sideband control register (PFEBSBCR) 11.2.32.1 Offset Register Offset PFEBSBCR 45Ch 11.2.32.2 Function This register contains control bits to provide programmability for AXI attributes of PFE HDBUS master interface. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 512 Control bit for snoopable attribute of read channel ARSNP 0b - Non snoopable 1b - Snoopable (default) Control bit for snoopable attribute of write channel AWSNP 0b - Non snoopable 1b - Snoopable (default) 6-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 513 Field Function EMI1_MDIO source select MDIOSEL 0b - Internally generated MDIO from SerDes directed to PFE (default) 1b - MDIO from external Ethernet PHY (EMI1_MDIO) directed to PFE 1-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 514 11.2.34.2 Function This register provides expansion bits for device control. 11.2.34.3 Diagram Bits Reset Bits Reset 11.2.34.4 Fields Field Function 0-31 32-bit spare contents 11.2.35 I2C debug mode control register (I2CDBGCR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 515 0b - I2C1 glitch filter disabled 1b - I2C1 glitch filter enabled I2C2 glitch filter enable I2C2 0b - I2C2 glitch filter disabled 1b - I2C2 glitch filter enabled 4-31 Reserved — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 516 0. SCRATCHRW2 - 32-bit boot location pointer (BOOTLOCPTR) SCRATCHRW3 - Register that indicates failures in SEC self tests (if any) conducted as part of secure boot flow SCRATCHRW4- Reserved QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 517 11.2.37.1 Offset Register Offset COREBCR 680h 11.2.37.2 Function This register provides expansion bits for device control. These bits are set on assertion of core reset. This register is blocked in PBI. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 518 This register provides the mechanism for setting an interrupt in the MSIR. When MSIIR is written, MSIIR[IBS] selects the shared interrupt bit in the selected MSIR register. MSIIR is primarily intended to support PCI Express MSIs. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 519 00001b - Set field SH1 (bit 30) 00010b - Set field SH2 (bit 29) 11111b - Set field SH31 (bit 0) 5-31 Reserved — 11.2.39 Shared message signaled interrupt register (PEX1MSIR) 11.2.39.1 Offset Register Offset PEX1MSIR 2004h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 520 11.2.39.3 Diagram Bits Reset Bits Reset 11.2.39.4 Fields Field Function 0-31 Message sharer n has a pending interrupt. NOTE: Bit 0 corresponds to SH0, bit 1 corresponds to SH1, and so on. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 521 • Two small sets of scratch registers: • One set of read / write scratch registers • One set of write-once / read scratch registers QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 522 Core Reset Status Register n (CRSTSR0) 0000_0000h 608h DMA Control Register (DMACR1) 0000_0000h 740h - 83Ch Topology Initiator Type n Register (TP_ITYP0 - TP_ITYP63) description. 844h Core Cluster n Topology Register (TP_CLUSTER1) description. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 523 The status of these bits depends on the sampling value driven on the pad. 12.3.2.3 Diagram Bits Reset Bits Reserved Reset 12.3.2.4 Fields Field Function Reserved — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 524 12.3.3.1 Offset Register Offset PORSR2 12.3.3.2 Function PORSR2 captures the values of the device's POR configuration pins. NOTE The status of these bits depends on the sampling value driven on the pad. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 525 Loaded with the value of the cfg_eng_use[2] pin at power-on ENG2 reset. Refer Transconductance selection control for details. 0b - Config pin was not set 1b - Config pin was set 7-31 Reserved — Reserved 12.3.4 Fuse Status Register (FUSESR) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 526 VID is not applicable for this chip, which means the boot software is not required to read this register and adjust voltage. 12.3.4.3 Diagram Bits Reset Bits Reserved Reset 12.3.4.4 Fields Field Function Reserved — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 527 VDD alternate voltage. This is a secondary voltage field for VDD. The field encodings are the same as DA_V , except 11111 is reserved.. DA_ALT_V 12-31 Reserved — 12.3.5 Device Disable Register 1 (DEVDISR1) 12.3.5.1 Offset Register Offset DEVDISR1 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 528 12.3.5.3 Diagram Bits Reset Bits Reset 12.3.5.4 Fields Field Function Pre-boot loader disable. 0b - Module is enabled 1b - Module is disabled Reserved — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 529 0b - Module is enabled 1b - Module is disabled 18-21 Reserved — SEC module disable. 0b - Module is enabled 1b - Module is disabled 23-31 Reserved — 12.3.6 Device Disable Register 2 (DEVDISR2) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 530 IP blocks that are not used when running an application. 12.3.6.3 Diagram Bits Reserved Reset Bits Reserved Reset 12.3.6.4 Fields Field Function 0-31 Reserved — 12.3.7 Device Disable Register 3 (DEVDISR3) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 531 IP blocks that are not used when running an application. 12.3.7.3 Diagram Bits Reserved Reset Bits Reserved Reset 12.3.7.4 Fields Field Function 0-31 Reserved — 12.3.8 Device Disable Register 4 (DEVDISR4) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 532 Power down for any module can be configured by programming the DCFG_DEVDISR register. If any module is powered down, then its data access as well as register access are not allowed. 12.3.8.3 Diagram Bits Reset Bits Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 533 IP Blocks disabled by setting the corresponding bit in the DEVDISR5 register must not be re-enabled. NOTE Power down for any module can be configured by programming the DCFG_DEVDISR register. If any module is QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 534 OCRAM1 disable OCRAM1 0b - Module is enabled 1b - Module is disabled OCRAM2 disable OCRAM2 0b - Module is enabled 1b - Module is disabled Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 535 1b - Module is disabled C1 disable. IIC1 0b - Module is enabled 1b - Module is disabled Cache coherent interconnect disable. CCI_400 0b - Module is enabled 1b - Module is disabled QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 536 MINOR_REV Reset 12.3.10.4 Fields Field Function Manufacturer ID MFR_ID 4-15 Chip Device ID SOC_DEV_ID 16-23 Various Personalities VAR_PER 0000_0001 LS1012A (Export controlled crypto hardware enabled) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 537 Minor Revision Number MINOR_REV 12.3.11 Reset Control Register (RSTCR) 12.3.11.1 Offset Register Offset RSTCR 12.3.11.2 Function The RSTCR allows software to control reset functions. 12.3.11.3 Diagram Bits Reserved Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 538 12.3.12.2 Function The RSTRQPBLSR contains status bits to record the reasons for RESET_REQ_B assertion. It excludes core watchdog timer sources. NOTE This register's code is valid only when RSTRQSR[PBL_RR] is set. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 539 Write 1 to each bit to clear this field. NOTE: See Error codes for details on the PBL error encodings. 15-31 Reserved — 12.3.13 Reset Request Mask Register (RSTRQMR1) 12.3.13.1 Offset Register Offset RSTRQMR1 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 540 Bits Reset Bits Reset 12.3.13.4 Fields Field Function 0-11 Reserved — ALTCBAR violation by PBL reset request mask ALTCBAR_MSK PBL error reset request event mask. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 541 0b - Core watchdog reset request can cause a reset request RST_MSK 1b - Core watchdog reset request cannot cause a reset request 23-31 Reserved — 12.3.14 Reset Request Status Register (RSTRQSR1) 12.3.14.1 Offset Register Offset RSTRQSR1 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 542 NOTE When RESET_REQ_B is selected, the SFP_RR bit is reserved and PBL_RR is required only in PBI phase and not in the RCW loading stage. 12.3.14.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 543 Core watchdog event reset request. CORE_WDOG1 0b - Core watchdog reset request from WDOG1 is not active _RST_RR 1b - Core watchdog reset request from WDOG1 is active Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 544 NOTE If a bit is changed from 1 to 0 outside of warm reset (at runtime), results are boundedly undefined for that core. 12.3.15.3 Diagram Bits Reserved Reset Bits Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 545 100h + (a × 4h) 12.3.16.2 Function RCWSR contains the Reset Configuration Word (RCW) information written with values read from flash memory by the device at power-on reset and read-only upon exiting reset. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 546 1FCh + (a × 4h) 12.3.17.2 Function The SCRATCHRWn provides read / write scratch register locations available to the user. NOTE When performing secure boot, these registers are defined as follows: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 547 Field Function 0-31 32-bit scratch contents 12.3.18 Scratch Read Register n (SCRATCHW1R1 - SCRATCHW 1R4) 12.3.18.1 Offset For a = 1 to 4: Register Offset SCRATCHW1Ra 2FCh + (a × 4h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 548 12.3.18.3 Diagram Bits Reset Bits Reset 12.3.18.4 Fields Field Function 0-31 32-bit scratch contents 12.3.19 Core Reset Status Register n (CRSTSR0) 12.3.19.1 Offset Register Offset CRSTSR0 400h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 549 This bit is cleared on a device power-on. Upon completion of power-on processing, this bit may be automatically set for a core if none of the conditions specified in the READY bit definition are true. 12.3.19.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 550 0b - Core 0 not ready 1b - Core 0 ready Reserved — Core was reset due to a PORESET RST_PORST 12.3.20 DMA Control Register (DMACR1) 12.3.20.1 Offset Register Offset DMACR1 608h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 551 10b - Reserved 11b - DMA's Channel may be initiated by EPU 2-31 Reserved — 12.3.21 Topology Initiator Type n Register (TP_ITYP0 - TP_ITYP6 12.3.21.1 Offset For a = 0 to 63: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 552 All encodings not listed below are reserved. 00000000b - Simple initiatior 00000010b - Arm Cortex A53 (disabled) 00000011b - Arm Cortex A53 (enabled) 12.3.22 Core Cluster n Topology Register (TP_CLUSTER1) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 553 End of Clusters - if the EOC field is non-zero, the register contains the information on the last cluster in the chip. 00 Not the last cluster 01,10,11 Last cluster in the chip Initiator Type Index for this cluster's fourth initiator Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 554 Provides a 6-bit index for accessing an entry stored in one of the TP_ITYPn registers. This index selects which of the 64 TP_ITYPn registers contains the identification information for this initiator. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 555 The RCPM module supports multithreaded core; however, the A53 core implemented on chip are single-threaded. The following table describes the mapping of the referenced RCPM thread and physical core to the Arm Cortex-A53 core: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 556 Instruction execution from the core. • LPM20 state wake up source is captured in Table 13-5 • Independent Device wake up from: • Unmasked interrupt configured in GIC-400 and RCPM registers • Unmasked critical interrupt QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 557 1. A resumable power state in the core indicates that the core can exit from a power managed state and return to Full On without the core being reset. Table 13-3 summarizes the device RCPM modes. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 558 RCPM interaction. The registers given below provides the different status of the core: • TWAITSR0: Status shows core is in the WFI state • POWMGTCSR: LPM20 request and status QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 559 To follow the LPM20 sequence in such cases, the core should be first brought out from the boot hold- off state. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 560 The modules which can be used as a wake up source are internal timers, internal and external interrupts. The following figure describes the sleep flow for the chip. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 561 In the chip, the Arm cluster does not support PH20 (retention) mode. As part of LPM20 sequence, the chip requests for cluster to enter into retention mode which it immediately acknowledges without actually going into retention mode. 13.1.7 Reset Modes QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 562 13.3 RCPM register descriptions This section identifies power management resources that are not included as part of a processor core or platform IP. 13.3.1 RCPM Memory map RCPM base address: 1EE_2000h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 563 13.3.2 Thread Wait status Register (TWAITSR) 13.3.2.1 Offset Register Offset TWAITSR 13.3.2.2 Function This register is used for reporting wait status per core. 13.3.2.3 Diagram Bits T31_T0 Reset Bits T31_T0 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 564 This register is used for entering the chip's LPM state. In addition, it provides status indicating successful entry into the corresponding power management state. NOTE The following table describes this register's bit settings. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 565 Previous LPM20 Status. It is used by software to know which state the chip was in before being wake up. Before software set POWMGTCSR[LPM20_REQ], we expect software w1c [P_LPM20_ST] Bit. P_LPM20_ST 0 Device was not in LPM20 state before being wake up by interrupt. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 566 IP blocks available as sources for wake-up events. For example, • Wake on LAN (magic packet) - Requires excluding the Ethernet controller from device LPM20 mode • Wake on GPIO - Requires excluding the GPIO controller from device LPM20 mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 567 — Reserved FlexTimer1 powerdown exception FlexTimer1 0b - FlexTimer1 powerdown during device LPM20 1b - FlexTimer1 is not powerdown during device LPM20 OCRAM1 powerdown exception Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 568 13.3.5 nIRQOUT interrupt mask register (nIRQOUTR) 13.3.5.1 Offset Register Offset nIRQOUTR 15Ch 13.3.5.2 Function The register masks the nIRQOUT Interrupt from GIC-400 for Sleep/LPM20 mode. 13.3.5.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 569 The register masks the nFIQOUT interrupt from GIC-400 for Sleep/LPM20 mode. The LPM20 FSM recognizes the corresponding core interrupt from GIC-400 and initiates a wake-up sequence provided the interrupt mask is not set. 13.3.6.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 570 The wake-up events are mapped to interrupt controller interrupts to generate a wake-up interrupt to the core. For information on operation entry or exit, refer Modes Entry and Exit for Power Management. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 571 • QoS Compliant with HGI 2.0 at any packet size • Two independent MAC ports: • Port 1 supports SGMII • Port 2 supports RGMII/SGMII • Includes JTAG and UART interfaces for debugging QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 572 MAC is provided. The MDIO ports are connected in the chip as follows: • MDIO1: It has connectivity for external off-chip PHY registers as well as on-chip SGMII1 PCS registers. The selection occurs based on the SCFG_MDIOSELCR[MDIOSEL] bit as follows: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 573 Chapter 14 Packet Forwarding Engine (PFE) • 0: MDIO from SerDes • 1: MDIO from external Ethernet PHY • MDIO2: It has connectivity for on-chip SGMII2 PCS registers. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 574 Functional description QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 575 The UART interface is point to point, meaning that only two UART devicedsscs are attached to the connecting signals. As shown in the figure below, each UART module consists of the following: • Receive and transmit buffers QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 576 • Software-programmable baud generators that divide the platform clock/2 by 1 to (2 - 1) and generate a 16x clock for the transmitter and receiver engines • Clear to send (CTS_B and ready to send (RTS_B) modem control functions QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 577 The DUART signals are described in the table below. NOTE Although the actual device signal names are prepended with the UART_ prefix as shown in the table, the abbreviated signal names are often used throughout this chapter. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 578 The table below provides a register summary with references to the section and page that contains detailed information about each register. Undefined byte address spaces within offset 0x000-0xFFF are reserved. 15.4.1 DUART Memory map DUART base address: 21C_0000h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 579 UART DMA status register (UDSR2) 15.4.2 UART divisor least significant byte register (UDLB1 - UDLB2) 15.4.2.1 Offset For a = 1 to 2: Register Offset UDLBa 400h + (a × 100h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 580 (Decimal) Decimal 9,600 032E 9597.666 0.0243 19,200 0197 19,195.33 0.0243 38,400 00CB 38,485.22 0.2219 57,600 0088 57,444.85 0.2694 115,200 0044 114,889.7 0.2694 230,400 0022 229,779.4 0.2694 15.4.2.3 Diagram Bits UDLB Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 581 Refer to the ULSR[OE] description, UART line status register (ULSR1 - ULSR2) . Note that these registers have same offset as the UTHRs. 15.4.3.3 Diagram Bits DATA Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 582 UART bus, and the first byte written to UTHR is the first byte onto the bus. UDSR[TXRDY_B] indicates when the FIFO is full. See UART DMA status register (UDSR1 - UDSR2) for more details. 15.4.4.3 Diagram Bits DATA Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 583 Equivalently, [UDMB||UDLB:0b0000] = platform clock frequency/2 ÷ desired baud rate. Baud rates that can be generated by specific input clock frequencies are shown in UART divisor least significant byte register (UDLB1 - UDLB2). 15.4.5.3 Diagram Bits UDMB Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 584 15.4.6.2 Function This register is accessible when ULCR[DLAB] = 0. The UIER gives the user the ability to mask specific UART interrupts to the programmable interrupt controller (PIC). 15.4.6.3 Diagram Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 585 This register is accessible when ULCR[DLAB] = 1. The UAFRs give software the ability to gate off the baud clock and write to each UARTn registers simultaneously with the same write operation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 586 15.4.8 UART FIFO control register (UFCR1 - UFCR2) 15.4.8.1 Offset For a = 1 to 2: Register Offset UFCRa 402h + (a × 100h) 15.4.8.2 Function This register is accessible when ULCR[DLAB] = 0. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 587 Transmitter FIFO reset 0b - No action 1b - Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0 Receiver FIFO reset Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 588 While this read transaction is occurring, the associated DUART serial channel records new interrupts, but does not change the contents of UIIR until the read access is complete. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 589 CTS_B input value Read the UMSR. changed since last read of UMSR 15.4.9.3 Diagram Bits Reset 15.4.9.4 Fields Field Function FIFOs enabled. Reflects the setting of UFCR[FEN] Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 590 UART bus are active. The software should not re-write the ULCR until the last STOP bit has been received and there are no new characters being transferred on the bus. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 591 0b - Send normal UTHR data onto the serial output (SOUT) signal 1b - Force logic 0 to be on the SOUT signal. Data in the UTHR is not affected Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 592 The ULSRs are read-only registers that monitor the status of the data transfer on the UART buses. To isolate the status bits from the proper character received through the UART bus, software should read the ULSR and then the URBR. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 593 FIFO). An attempt to resynchronize occurs after a framing error. The UART assumes that the framing error (due to a logic 0 being read when a logic 1 (STOP) was Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 594 This register is accessible when ULCR[DLAB] = x. The USCR registers are for debugging software or the DUART hardware. The USCRs do not affect the operation of the DUART. 15.4.12.3 Diagram Bits DATA Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 595 Table 15-6. UDSR[TXRDY] Set Conditions DMA Mode Meaning TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR. TXRDY is set when the transmitter FIFO is full. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 596 FIFO or URBR. RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains cleared until the receiver FIFO is empty. 15.4.13.3 Diagram Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 597 Figure 15-2. UART bus interface transaction protocol example A standard UART bus transfer is composed of either three or four parts: • START bit • Data transfer bits (least-significant bit is first data bit on the bus) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 598 When receiving data, a parity error can occur if an unexpected parity value is detected. See UART line status register (ULSR1 - ULSR2). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 599 UMSR[CTS]. The transmitter SOUT is set to a logic 1 and the receiver SIN is disconnected. The output of the transmitter shift register is looped back into the receiver shift register input. The CTS_B (input signal) is disconnected, RTS_B is QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 600 In FIFO mode, ULSR[PE] is set when the character with the error is at the top of the FIFO. ULSR[PE] is cleared when ULSR is read or when a new character is loaded into the URBR. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 601 The character time-out interrupt (controlled by UIIR[IIDn]) is cleared when the URBR is read. See UART interrupt ID register (UIIR1 - UIIR2) for more information. The UIIR[FE] bit indicates if FIFO mode is enabled. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 602 3. Set the data attributes and control bits of the external modem or peripheral device. 4. Set the interrupt enable register (UIER). 5. To start a write transfer, write to the UTHR. 6. Poll UIIR, if the interrupts generated by the DUART are masked. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 603 16.1.2 LS1012A DMAMUX module special consideration 16.1.2.1 eDMA and DMAMUX The device contains one eDMA and two DMAMUX modules. The eDMA module implements the following parameter settings in the chip: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 604 As shown in the figure below, request from MUX1 can be mapped to any of the first 16 DMA channels and from MUX2, to any of the lower 16 DMA channels. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 605 DMA transfer request from EPU Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 606 SAI3 Rx FlexTimer1[0] SAI3 Tx FlexTimer1[1] SAI2 Rx FlexTimer1[2] SAI2 Tx FlexTimer1[3] SAI1 Rx Reserved SAI1 Tx Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 607 The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 32 DMA channels. See the chip-specific information to know the detailed source numbers. This process is illustrated in the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 608 • Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 16.2.3 Modes of operation The following operating modes are available: • Disabled mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 609 (In bits) Channel Configuration register (CHCFG3) Channel Configuration register (CHCFG2) Channel Configuration register (CHCFG1) Channel Configuration register (CHCFG0) Channel Configuration register (CHCFG7) Channel Configuration register (CHCFG6) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 610 Channel Configuration register (CHCFG30) Channel Configuration register (CHCFG29) Channel Configuration register (CHCFG28) 16.4.1.2 Channel Configuration register (CHCFG0 - CHCFG31) 16.4.1.2.1 Offset Register Offset CHCFG3 CHCFG2 CHCFG1 CHCFG0 CHCFG7 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 611 Setting multiple CHCFG registers with the same source value will result in unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). Before changing the source settings, a DMA channel must be disabled via CHCFGn[ENBL]. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 612 However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMAMUX may be changed during the normal operation of the system. The DMAMUX channels implement only the normal routing functionality. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 613 In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 614 *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 615 7. This example assumes channel 8 doesn't have triggering capability. 2. Write 0x00 to CHCFG8. 3. Write 0x87 to CHCFG8. The following code example illustrates steps 2 and 3 above: In File registers.h: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 616 *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 617 The hardware microarchitecture includes: • A DMA engine that performs: • Source address and destination address calculations • Data-movement operations • Local memory containing transfer control descriptors for each of the 32 channels QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 618 After a channel is activated, it runs until the minor loop is Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 619 It is intended for use in applications where the data size to be transferred is statically known and not defined within the transferred data itself. The eDMA module features: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 620 • Programmable support for scatter/gather DMA processing • Support for complex data structures In the discussion of this module, n is used to reference the channel number. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 621 0, channel 1, ... channel 31. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 17.4.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 622 • For 8-bit registers, the lower address byte is read as the most significant byte. • For 16-bit registers, the lower address word is read as the most significant word. The following figure provides examples of this. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 623 Error Register (ERR) 0000_0000h Hardware Request Status Register (HRS) 0000_0000h 100h Channel Priority Register (DCHPRI3) 101h Channel Priority Register (DCHPRI2) 102h Channel Priority Register (DCHPRI1) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 624 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBY TES_MLNO) description. 1008h TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 625 1038h TCD Last Destination Address Adjustment/Scatter Gather Address (TCD1_DLASTSGA) description. 103Ch TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD1_BITER_ELINKNO) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 626 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD3_NBYTES_MLOFFNO) description. 1068h TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD3_NBYTES_MLOFFYES) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 627 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD4_BITER_ELINKNO) description. 109Ch TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD4_BITER_ELINKYES) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 628 Offset Disabled) (TCD6_NBYTES_MLOFFNO) description. 10C8h TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD6_NBYTES_MLOFFYES) description. 10CCh TCD Last Source Address Adjustment (TCD6_SLAST) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 629 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD7_BITER_ELINKNO) description. 10FCh TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD7_BITER_ELINKYES) description. 10FEh TCD Control and Status (TCD7_CSR) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 630 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD9_NBYTES_MLOFFYES) description. 112Ch TCD Last Source Address Adjustment (TCD9_SLAST) description. 1130h TCD Destination Address (TCD9_DADDR) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 631 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD10_BITER_ELINKYES) description. 115Eh TCD Control and Status (TCD10_CSR) description. 1160h TCD Source Address (TCD11_SADDR) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 632 TCD Last Source Address Adjustment (TCD12_SLAST) description. 1190h TCD Destination Address (TCD12_DADDR) description. 1194h TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD12_CITER_ELINKNO) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 633 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD13_BITER_ELINKYES) description. 11BEh TCD Control and Status (TCD13_CSR) description. 11C0h TCD Source Address (TCD14_SADDR) description. 11C4h TCD Transfer Attributes (TCD14_ATTR) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 634 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD15_CITER_ELINKNO) description. 11F4h TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD15_CITER_ELINKYES) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 635 TCD Control and Status (TCD16_CSR) description. 1220h TCD Source Address (TCD17_SADDR) description. 1224h TCD Transfer Attributes (TCD17_ATTR) description. 1226h TCD Signed Source Address Offset (TCD17_SOFF) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 636 Disabled) (TCD18_CITER_ELINKNO) description. 1254h TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD18_CITER_ELINKYES) description. 1256h TCD Signed Destination Address Offset (TCD18_DOFF) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 637 TCD Transfer Attributes (TCD20_ATTR) description. 1286h TCD Signed Source Address Offset (TCD20_SOFF) description. 1288h TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD20_NB YTES_MLNO) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 638 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD21_CITER_ELINKYES) description. 12B6h TCD Signed Destination Address Offset (TCD21_DOFF) description. 12B8h TCD Last Destination Address Adjustment/Scatter Gather Address (TCD21_DLASTSGA) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 639 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD23_NB YTES_MLNO) description. 12E8h TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD23_NBYTES_MLOFFNO) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 640 1318h TCD Last Destination Address Adjustment/Scatter Gather Address (TCD24_DLASTSGA) description. 131Ch TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD24_BITER_ELINKNO) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 641 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD26_NBYTES_MLOFFNO) description. 1348h TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD26_NBYTES_MLOFFYES) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 642 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD27_BITER_ELINKNO) description. 137Ch TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD27_BITER_ELINKYES) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 643 Offset Disabled) (TCD29_NBYTES_MLOFFNO) description. 13A8h TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD29_NBYTES_MLOFFYES) description. 13ACh TCD Last Source Address Adjustment (TCD29_SLAST) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 644 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD30_BITER_ELINKNO) description. 13DCh TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD30_BITER_ELINKYES) description. 13DEh TCD Control and Status (TCD30_CSR) description. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 645 Disabled) (TCD31_BITER_ELINKNO) description. 13FCh TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD31_BITER_ELINKYES) description. 13FEh TCD Control and Status (TCD31_CSR) description. 17.4.6.2 Control Register (CR) 17.4.6.2.1 Offset Register Offset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 646 (TCDn_DADDR) upon minor loop completion, and the sign extended minor loop offset value (MLOFF). The same offset value (MLOFF) is used for both source and destination minor loop offsets. When either QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 647 (DMAx_ES) and generating an optional error interrupt. 16-20 Reserved — Channel Group 1 Priority GRP1PRI Group 1 priority level when fixed priority group arbitration is enabled. Reserved — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 648 1b - When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. Reserved — Reserved 17.4.6.3 Error Status Register (ES) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 649 0b - No ERR bits are set. 1b - At least one ERR bit is set indicating a valid error exists that has not been cleared. 1-14 Reserved — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 650 1b - The last recorded error was a bus error on a source read Destination Bus Error 0b - No destination bus error 1b - The last recorded error was a bus error on a destination write QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 651 NOTE Disable a channel's hardware service request at the source before clearing the channel's ERQ bit. 17.4.6.4.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 652 0b - The DMA request signal for the corresponding channel is disabled ERQ16 1b - The DMA request signal for the corresponding channel is enabled Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 653 1b - The DMA request signal for the corresponding channel is enabled Enable DMA Request 0 0b - The DMA request signal for the corresponding channel is disabled ERQ0 1b - The DMA request signal for the corresponding channel is enabled QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 654 0b - The error signal for corresponding channel does not generate an error interrupt EEI31 1b - The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 30 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 655 0b - The error signal for corresponding channel does not generate an error interrupt EEI14 1b - The assertion of the error signal for corresponding channel generates an error interrupt request Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 656 0b - The error signal for corresponding channel does not generate an error interrupt EEI0 1b - The assertion of the error signal for corresponding channel generates an error interrupt request 17.4.6.6 Set Enable Request Register (SERQ) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 657 0b - Set only the ERQ bit specified in the SERQ field SAER 1b - Set all bits in ERQ Reserved — Set Enable Request SERQ Sets the corresponding bit in ERQ. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 658 Disable a channel's hardware service request at the source before clearing the channel's ERQ bit. 17.4.6.7.3 Diagram Bits Reset 17.4.6.7.4 Fields Field Function No Op enable 0b - Normal operation Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 659 In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write. Reads of this register return all zeroes. 17.4.6.8.3 Diagram Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 660 In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write. Reads of this register return all zeroes. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 661 INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 662 0b - Clear only the INT bit specified in the CINT field CAIR 1b - Clear all bits in INT Reserved — Clear Interrupt Request CINT Clears the corresponding bit in INT 17.4.6.11 Clear Error Register (CERR) 17.4.6.11.1 Offset Register Offset CERR QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 663 CAEI 1b - Clear all bits in ERR Reserved — Clear Error Indicator CERR Clears the corresponding bit in ERR 17.4.6.12 Set START Bit Register (SSRT) 17.4.6.12.1 Offset Register Offset SSRT QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 664 0b - Set only the TCDn_CSR[START] bit specified in the SSRT field SAST 1b - Set all bits in TCDn_CSR[START] Reserved — Set START Bit SSRT Sets the corresponding bit in TCDn_CSR[START] 17.4.6.13 Clear DONE Status Bit Register (CDNE) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 665 0b - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field CADN 1b - Clears all bits in TCDn_CSR[DONE] Reserved — Clear DONE Bit CDNE Clears the corresponding bit in TCDn_CSR[DONE] QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 666 INT register. 17.4.6.14.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 667 0b - The interrupt request for corresponding channel is cleared INT17 1b - The interrupt request for corresponding channel is active Interrupt Request 16 0b - The interrupt request for corresponding channel is cleared Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 668 1b - The interrupt request for corresponding channel is active Interrupt Request 0 0b - The interrupt request for corresponding channel is cleared INT0 1b - The interrupt request for corresponding channel is active QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 669 A zero in any bit position has no affect on the corresponding channel's current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 670 1b - An error in this channel has occurred Error In Channel 23 0b - An error in this channel has not occurred ERR23 1b - An error in this channel has occurred Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 671 ERR7 1b - An error in this channel has occurred Error In Channel 6 0b - An error in this channel has not occurred ERR6 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 672 DMA's arbitration logic. This view into the hardware request signals may be used for debug purposes. NOTE These bits reflect the state of the request as seen by the arbitration logic. Therefore, this status is affected by the ERQ bits. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 673 Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0b - A hardware service request for channel 27 is not present Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 674 0b - A hardware service request for channel 19 is not present 1b - A hardware service request for channel 19 is present Hardware Request Status Channel 18 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 675 0b - A hardware service request for channel 11 is not present 1b - A hardware service request for channel 11 is present Hardware Request Status Channel 10 HRS10 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 676 0b - A hardware service request for channel 3 is not present 1b - A hardware service request for channel 3 is present Hardware Request Status Channel 2 HRS2 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 677 105h DCHPRI5 106h DCHPRI4 107h DCHPRI11 108h DCHPRI10 109h DCHPRI9 10Ah DCHPRI8 10Bh DCHPRI15 10Ch DCHPRI14 10Dh DCHPRI13 10Eh DCHPRI12 10Fh DCHPRI19 110h DCHPRI18 111h Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 678 GRPPRI bits are not affected by writes to the DCHPRIn registers. The group priority is assigned in the DMA control register. 17.4.6.17.3 Diagram Bits GRPPRI CHPRI Register Reset reset values. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 679 17.4.6.17.5 Fields Field Function Enable Channel Preemption. This field resets to 0. 0b - Channel n cannot be suspended by a higher priority channel's service request. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 680 ID and protection level are captured when the TCDn.CSR control attributes are written. Although the scatter/gather operation can change the contents of TCDn_CSR, that operation does not affect the DCHMID n registers. 17.4.6.18.3 Diagram Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 681 17.4.6.19 TCD Source Address (TCD0_SADDR - TCD31_SADDR) 17.4.6.19.1 Offset For n = 0 to 31: Register Offset TCDn_SADDR 1000h + (n × 20h) 17.4.6.19.2 Function This register contains the source address of the transfer. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 682 17.4.6.20 TCD Transfer Attributes (TCD0_ATTR - TCD31_ATTR) 17.4.6.20.1 Offset For n = 0 to 31: Register Offset TCDn_ATTR 1004h + (n × 20h) 17.4.6.20.2 Diagram Bits SMOD SSIZE DMOD DSIZE Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 683 DSIZE See the SSIZE definition 17.4.6.21 TCD Signed Source Address Offset (TCD0_SOFF - TCD31_ SOFF) 17.4.6.21.1 Offset For n = 0 to 31: Register Offset TCDn_SOFF 1006h + (n × 20h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 684 TCD word 2 is defined as follows if: • Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 685 17.4.6.23 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD31_NBYTES_MLOFFNO) 17.4.6.23.1 Offset For n = 0 to 31: Register Offset TCDn_NBYTES_MLOFF 1008h + (n × 20h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 686 0b - The minor loop offset is not applied to the DADDR 1b - The minor loop offset is applied to the DADDR 2-31 Minor Byte Transfer Count NBYTES Number of bytes to be transferred in each service request of the channel. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 687 If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 688 TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 17.4.6.25 TCD Last Source Address Adjustment (TCD0_SLAST - TCD31_SLAST) 17.4.6.25.1 Offset For n = 0 to 31: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 689 17.4.6.26 TCD Destination Address (TCD0_DADDR - TCD31_DADDR) 17.4.6.26.1 Offset For n = 0 to 31: Register Offset TCDn_DADDR 1010h + (n × 20h) 17.4.6.26.2 Function This register contains the destination address of the transfer. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 690 Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD31_CITER_ ELINKYES), but its fields are defined differently based on the state of the ELINK field. If the ELINK field is cleared, this register is defined as follows. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 691 17.4.6.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD31_CI TER_ELINKYES) 17.4.6.28.1 Offset For n = 0 to 31: Register Offset TCDn_CITER_ELINKYE 1014h + (n × 20h) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 692 CITER field from the Beginning Iteration Count (BITER) field. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 693 Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. 17.4.6.30 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA - TCD31_DLASTSGA) 17.4.6.30.1 Offset For n = 0 to 31: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 694 The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. 17.4.6.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_BITER_ELINKNO - TCD3 1_BITER_ELINKNO) 17.4.6.31.1 Offset For n = 0 to 31: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 695 CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 696 CITER field. 0b - The channel-to-channel linking is disabled 1b - The channel-to-channel linking is enabled Reserved — Link Channel Number LINKCH Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 697 17.4.6.33.1 Offset For n = 0 to 31: Register Offset TCDn_CSR 101Eh + (n × 20h) 17.4.6.33.2 Diagram Bits Reset 17.4.6.33.3 Fields Field Function Bandwidth Control Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 698 Disable Request DREQ If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current major iteration count reaches zero. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 699 17.5.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 700 The following diagram illustrates the second part of the basic data flow: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 701 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 702 Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 703 Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 704 If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 705 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 706 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 707 The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 708 The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 17.6.3 Arbitration mode considerations This section discusses arbitration considerations for the eDMA. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 709 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000. The address offsets are QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 710 Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop complete. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 711 Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 → third iteration of the minor loop. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 712 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 713 The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop- QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 714 The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 715 TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 716 This section provides recommended methods to change the programming model during channel execution. 17.6.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 717 TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the The TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJORELINK] bit. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 718 1. When the descriptors are built, write a unique TCD ID in the TCDn_CSR[MAJORLINKCH] field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCDn_CSR[DREQ] bit. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 719 If ESG = 0b, read the 32 bit TCDn_DLASTSGA field. If ESG = 0b and the TCDn_DLASTSGA did not change, the attempted dynamic link did not succeed (the channel was already retiring). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 720 TXFIFO upon the request. If the user needs to suspend the DMA/SPI transfer loop, perform the following steps: 1. Disable the DMA service request at the source by writing 0 to SPI_RSER[TFFF_RE]. Confirm that SPI_RSER[TFFF_RE] is 0. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 721 DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present, disable the DMA channel by clearing the channel's ERQ bit. If a service request is present, wait until the request has been processed and the HRS bit reads zero. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 722 Initialization/application information QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 723 Table 18-2. LS1012A eSDHC signals LS1012A signal name eSDHC module signal SDHC1_CLK / SDHC2_CLK SDHC_CLK SDHC1_CMD / SDHC2_CMD SDHC_CMD SDHC1_DAT[3:0] / SDHC2_DAT[3:0] SDHC_DAT[3:0] SDHC1_CD_B SDHC_CD_B SDHC1_WP SDHC_WP Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 724 However, for eMMC 1.8V, the IO voltage can be set to 1.8V by default. • There is no card detect pin for SDHC2 interface since only embedded devices are supported (eSDIO, eMMC). Software needs to assume card is always present. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 725 The eSDHC acts as a bridge, passing host bus transactions to SD/SDIO cards by sending commands and performing data accesses to or from the cards. It handles the SD/SDIO protocol at the transmission level. The figure below shows connection of the eSDHC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 726 Supply CoreNet Register Bus Figure 18-1. System connection of the eSDHC NOTE The card slot is not valid for embedded devices. The figure below is a high-level block diagram of eSDHC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 727 • Conforms to the SD Host controller standard specification version 3.0, including test event register support • Compatible with the eMMC system specification version 4.5 • Compatible with the SD memory card specification version 3.01, and supports the high capacity SD memory card QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 728 18.2.2.1 Data transfer modes The eSDHC can select the following modes for data transfer: • SD 1 bit • SD 4 bit • eMMC 1 bit • eMMC 4 bit • Identification mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 729 • SDHC_DAT[3:0] performs data transfers between the eSDHC and the card. • SDHC_CD_B and SDHC_WP are card detection and write protection signals from the socket. • SDHC_VS is an output signal used to control the voltage of external SD bus supply. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 730 The table below shows the memory-mapped registers of the eSDHC module and lists the offset, name, and a cross-reference to the complete description of each register. These register only support 32-bit accesses. 18.4.1 eSDHC Memory map ESDHC1 base address: 156_0000h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 731 Tuning block status register (TBSTAT) 0000_0000h 128h Tuning block pointer register (TBPTR) 0000_0000h 140h SD direction control register (SDDIRCTL) 0000_0001h 144h SD Clock Control Register (SDCLKCTL) 0000_0000h 40Ch eSDHC control register (ESDHCCTL) 0000_0000h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 732 Function 0-31 DMA system address / Block attributes 2 DS_ADDR This register contains the physical system memory address used for DMA transfers or second argument for Auto CMD23. SDMA system address: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 733 BLKATTR 18.4.3.2 Function The BLKATTR is used to configure the number of data blocks and the number of bytes in each block. 18.4.3.3 Diagram Bits BLKCNT Reset Bits Reserved BLKSIZE Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 734 000000000001b - 1 byte 000000000010b - 2 bytes 000000000011b - 3 bytes 000000000100b - 4 bytes 000111111111b - 511 bytes 001000000000b - 512 bytes 100000000000b - 2048 bytes 18.4.4 Command argument register (CMDARG) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 735 Command argument. The SD/eMMC command argument is specified as bits 39-8 of the command format in the SD or eMMC Specification. This register is write protected when PRSSTAT[CIHB] is set. CMDARG 18.4.5 Transfer type register (XFERTYP) 18.4.5.1 Offset Register Offset XFERTYP QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 736 The table below shows the relationship between the command index check enable and the command CRC check enable, in regards to the response type bits as well as the name of the response type. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 737 • The CRC field for R3 and R4 is expected to be all 1 bits. The CRC check should be disabled for these response types. 18.4.5.3 Diagram Bits Reset Bits Reset 18.4.5.4 Fields Field Function Reserved. — Command index CMDINX Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 738 The number of bits checked by the CRC field value changes according to the length of the response. (Refer to RSPTYP[1:0] and Table 18-6.) 0b - Disable 1b - Enable Reserved. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 739 If ADMA data transfer is more than 65535 blocks, this bit shall be set to 0. In this case, data transfer length is designated by Descriptor Table. 0b - Disable 1b - Enable Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 740 18.4.6 Command response 0 register (CMDRSP0) 18.4.6.1 Offset Register Offset CMDRSP0 18.4.6.2 Function The CMDRSP0 is used to store part 0 of the response bits from the card. 18.4.6.3 Diagram Bits CMDRSP0 Reset Bits CMDRSP0 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 741 18.4.7 Command response 1 register (CMDRSP1) 18.4.7.1 Offset Register Offset CMDRSP1 18.4.7.2 Function The CMDRSP1 is used to store part 1 of the response bits from the card. 18.4.7.3 Diagram Bits CMDRSP1 Reset Bits CMDRSP1 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 742 18.4.8 Command response 2 register (CMDRSP2) 18.4.8.1 Offset Register Offset CMDRSP2 18.4.8.2 Function The CMDRSP2 is used to store part 2 of the response bits from the card. 18.4.8.3 Diagram Bits CMDRSP2 Reset Bits CMDRSP2 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 743 OCR register for memory R[39:8] CMDRSP0 R4 (OCR register) OCR register for I/O R[39:8] CMDRSP0 R5, R5b SDIO response R[39:8] CMDRSP0 R6 (Publish RCA) New Published RCA[31:16] and card R[39:9] CMDRSP0 status[15:0] QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 744 When the eSDHC modifies part of the command response registers (CMDRSP n ), as shown in the table above, it preserves the unmodified bits. 18.4.9.3 Diagram Bits CMDRSP3 Reset Bits CMDRSP3 Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 745 Offset DATPORT 18.4.10.2 Function The DATPORT is a 32-bit data port register used to access the internal buffer. Byte access is not allowed. 18.4.10.3 Diagram Bits DATCONT Reset Bits DATCONT Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 746 18.4.11.1 Offset Register Offset PRSSTAT 18.4.11.2 Function The host driver can get the status of the eSDHC from the PRSSTAT, which is a 32-bit, read-only register. 18.4.11.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 747 (IRQSTAT). Changing from a 1 to 0 generates a card removal interrupt in the interrupt status register (IRQSTAT). A write to the force event register (FEVT) does not effect this bit. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 748 This status is useful for the host driver in determining when to issue commands during write busy state. 0b - No valid data Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 749 Changing this bit from 1 to 0 generate a transfer complete interrupt in the interrupt status register (IRQSTAT). 0b - DAT line inactive 1b - DAT line active Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 750 3. If the host driver issues a suspend command and the SD card does not accept it, the continue request should be used to restart the transfer. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 751 SDHC_CLK toggling. When the wakeup feature is not enabled, the SDHC_CLK must be active in order to assert the card insertion status and the eSDHC interrupt. 0b - Disable 1b - Enable Wakeup event enable on card interrupt Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 752 SD bus clock to pause the read operation during block gap. In the case of write transfers in which the host driver writes data to the data port register, the host driver should set this bit Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 753 Possible Data transfer widths are 1-bit, 4-bits, and 8-bits. 00b - 1-bit mode 01b - 4-bit mode 10b - 8-bit mode 11b - Reserved Reserved. — QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 754 Register Select field in eSDHC Control register. Other bits of the register remain unaffected by clock register select value. 18.4.13.3 Diagram Bits Reset Bits Reset 18.4.13.4 Fields Field Function Reserved. — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 755 Removal bits in Interrupt Status Register. Software should issue partial reset(Reset for Command and Reset for Data) instead of Reset for All, if it wants to reset eSDHC without clearing these Interrupt Status Register bits. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 756 Divisor. This register is used to provide a more exact divisor to generate the desired SD clock frequency. Note the divider can even support odd divisor without deterioration of duty cycle. The settings are as following: 0000b - Divisor by 1 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 757 SDCLK is stopped (stop at SDCLK=0). If PRSSTAT[CINS] is cleared, this bit should be cleared by the host driver to save power. 29-31 Reserved. — 18.4.14 System Control Register when ESDHCCTL[CRS=1] (SYSCTL_ESDHCCTL_CRS_1) 18.4.14.1 Offset Register Offset SYSCTL_ESDHCCTL_ CRS_1 18.4.14.2 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 758 Register bits of type R, RW, RW1C are cleared. During its initialization, the host driver should set this bit RSTA to 1 to reset the eSDHC. The eSDHC should reset this bit to 0 when the capabilities registers are valid Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 759 0x01 Base clock divided by 2 0x00 Reserved The frequency of SDCLK is set by the following formula: Clock Frequency = (Base Clock) / (divisor) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 760 CINT bit will be asserted again Table 18-8. eSDHC Status for Command Timeout Error/Command Complete Bit Combinations Command Complete Command Timeout Error Meaning of the Status Response not received within 64 SDCLK cycles Response received QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 761 Bits Reset 18.4.15.4 Fields Field Function Reserved. — Register access timeout error. This bit indicate that register access has timed-out. 0b - No timeout error Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 762 Command index error. Occurs if a command index error occurs in the command response. 0b - No error 1b - Error Command end bit error. Occurs when detecting that the end bit of a command response is 0. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 763 Software should check Card Inserted in Present State register to confirm card insertion/removal status. 0b - Card state unstable or inserted Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 764 Command complete. This bit is set when the end bit of the command response is received (except Auto CMD12). Refer to PRSSTAT[CIHB]. 0b - Command not complete 1b - Command complete QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 765 • To detect a CMD line conflict, the host driver must set both IRSTAT[CTOESEN] and IRSTAT[CCESEN] to 1. 18.4.16.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 766 Command end bit error status enable. CEBESEN 0b - Masked 1b - Enabled Command CRC error status enable. CCESEN 0b - Masked 1b - Enabled Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 767 Block gap event status enable. BGESEN 0b - Masked 1b - Enabled Transfer complete status enable. TCSEN 0b - Masked 1b - Enabled Command complete status enable. CCSEN 0b - Masked 1b - Enabled QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 768 18.4.17.3 Diagram Bits Reset Bits Reset 18.4.17.4 Fields Field Function Reserved. — Register timeout error interrupt enable 0b - Masked Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 769 Command timeout error interrupt enable. CTOEIEN 0b - Masked 1b - Enabled 16-18 Reserved. — Re-tuning event interrupt enable 0b - Masked RTEIEN 1b - Enabled 20-22 Reserved. — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 770 1b - Enabled Command complete interrupt enable. CCIEN 0b - Masked 1b - Enabled 18.4.18 Auto CMD Error Status Register / System Control 2 Register (AUTOCERR_SYSCTL2) 18.4.18.1 Offset Register Offset AUTOCERR_SYSCTL2 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 771 An Auto CMD12 error interrupt is generated when one of the error bits (0-4) is set to 1. The command not issued by Auto CMD12 Error does not generate an interrupt. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 772 The result of tuning is indicated to sampling clock select EXTN field. Tuning procedure is aborted by writing 0. 0b - Not tuned or tuning not compelted 1b - Execute tuning 10-12 Reserved. — Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 773 1, other error status bits (1-4) have no meaning. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 0b - Executed 1b - Not executed 18.4.19 Host controller capabilities register (HOSTCAPBLT) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 774 64-bit system bus support. This bit indicates that system supports 64-bit address descriptor mode and is connected to 64-bit adress system bus. SBS64B 0b - 64-bit system bus not supported 1b - 64-bit system bus supported Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 775 The buffer should transfer block size without wait cycles. 000b - 512 bytes 001b - 1024 bytes 010b - 2048 bytes 011-111b - Reserved 16-31 Reserved. — 18.4.20 Watermark level register (WML) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 776 Max write burst length. Burst length desirable for write on system bus when DMA is used. This is the maximum burst length, actual burst length may be less than this depending on other factors, such as WR_BRST_LEN block boundary Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 777 CPU polling mode. RD_WML 0000000b - 128 words 0000001b - 1 word 0000010b - 2 words 1111111b - 127 words 18.4.21 Force event register (FEVT) 18.4.21.1 Offset Register Offset FEVT QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 778 Reserved. — Force event DMA error. Forces the IRQSTAT[DMAE] to be set. FEVTDMAE Reserved. — Force event ADMA error. Forces the IRQSTAT[ADMAE] to be set. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 779 Force event Auto CMD12 CRC error. Forces AUTOC12ERR[AC12CE] to be set. FEVTAC12CE Force event Auto CMD12 time out error. Forces the AUTOC12ERR[AC12TOE] to be set. FEVTAC12TOE Force event Auto CMD12 not executed. Forces AUTOC12ERR[AC12NE] to be set. FEVTAC12NE QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 780 Current descriptor address on which ADMA error occured DATA_XFER (data transfer) Current descriptor address on which ADMA error occured WAIT_STOP (Wait for ADMA to stop) Current descriptor address on which ADMA error occured QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 781 ADMA error state (when ADMA error is occurred). This field indicates the state of the ADMA when an error has occurred during an ADMA data transfer. Refer to the table above for more details. ADMAES QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 782 It can be accessed only when no transaction is executing (that is, after a transaction has stopped). The host driver should initialize this register before starting an ADMA transaction. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 783 00000000b - eSDHC Version 1.0 00010000b - eSDHC Version 2.0 00010001b - eSDHC Version 2.1 00010010b - eSDHC Version 2.2 00010011b - eSDHC Version 2.3 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 784 18.4.25 DMA error address register (DMAERRADDR) 18.4.25.1 Offset Register Offset DMAERRADDR 104h 18.4.25.2 Function The DMAERRADDR contains the address of the transaction on which DMA error occured. 18.4.25.3 Diagram Bits DMA_ADDRn Reset Bits DMA_ADDRn Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 785 The DMAERRATTR contains attributes of the transaction on which DMA error occured. 18.4.26.3 Diagram Bits Reserved Reset Bits DMA_SIZE DMA_LEN Reserved Reset 18.4.26.4 Fields Field Function 0-24 Reserved. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 786 The value in this register is the power-on-reset value, and does not change with a software reset. Any write to this register is ignored. 18.4.27.3 Diagram Bits Reserved Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 787 0b - SDR104 not supported SDR104 1b - SDR104 supported SDR50 support. This bit indicates whether the eSDHC supports the SDR50. 0b - SDR50 not supported SDR50 1b - SDR50 supported QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 788 Writing or reading to reserved fields of this register does not guarantee specific values will be written or read. 18.4.28.3 Diagram Bits Reset Bits Reset 18.4.28.4 Fields Field Function Reserved. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 789 11b - SW tuning mode - Software tuning mode where start and end point of data window needs to be programmed in TBPTR register and use software timer for re-tuning 18.4.29 Tuning block status register (TBSTAT) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 790 This register contains the status of the tuning block. 18.4.29.3 Diagram Bits TB_STATUS Reset Bits TB_STATUS Reset 18.4.29.4 Fields Field Function 0-31 Tuning Status. TB_STATUS 18.4.30 Tuning block pointer register (TBPTR) 18.4.30.1 Offset Register Offset TBPTR 128h QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 791 Tuning window start pointer. Selects window start pointer for software tuning mode (when TBCTL[TB_MODE]=3). TB_WNDW_ST RT_PTR Reserved. — 25-31 Tuning window start pointer. Selects window end pointer for software tuning mode (when TBCTL[TB_MODE]=3) TB_WNDW_EN D_PTR QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 792 000b - No turnaround time required 001b - 1 SD clock period for turnaround 010b - 2 SD clock periods for turnaround ... 111b - 7 SD clock periods for turnaround QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 793 18.4.32 SD Clock Control Register (SDCLKCTL) 18.4.32.1 Offset Register Offset SDCLKCTL 144h 18.4.32.2 Function This register contains fileds for controlling SD external and loopback clock. 18.4.32.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 794 1b - Command logic clock is 25% shifted early from data logic clock Reserved. — 18-19 Reserved. — 20-31 Reserved. — 18.4.33 eSDHC control register (ESDHCCTL) 18.4.33.1 Offset Register Offset ESDHCCTL 40Ch QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 795 This bit is cleared when a command Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 796 1b - It is safe to read more bytes that were intended. 30-31 Reserved. — 18.5 Functional description The eSDHC block is partitioned in five major sub-blocks as shown in Figure 18-2. • SD interface and control unit QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 797 FIFO to store transfer data. It controls the data transfer per-block basis in the CPU polling mode. • DMA block This sub-block generates DMA transactions on system bus to transfer the data between system memory and data buffer. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 798 Registers SD Bus Data Buffer SD Control & I/F System Bus Internal Figure 18-3. eSDHC buffer scheme There are two transfer modes to access the data buffer: • CPU polling mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 799 18.5.1.1.2 Read operation sequence There are two ways to read data from the buffer when the user transfers data to the card: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 800 (DATPORT) write to make it word aligned. For this example, 3 bytes should be stuffed. eSDHC will transfer only the required number of bytes to the card and ignore the stuff bytes as shown in the figure below. Read operation is similar. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 801 18-5. And, data transfer with byte stuffing disabled (when DMACTL[PAD_DIS]=1) is shown in Figure 18-6. Transfer with byte stuffing disabled eliminates the software overhead of byte stuffing. Driver may program DMA Control register accordingly. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 802 Functional description Card memory System memory eSDHC First block data Second block data Figure 18-5. Byte stuffing for DMA mode when DMACTL[PAD_DIS]=0 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 803 Second option is to add dummy data in the last block to fill the block size provided the card manages the removal of the dummy data. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 804 32-bytes are sent in Byte Transfer Mode SDIO Data SDIO Data SDIO Data SDIO Data CMD53 CMD53 Block 1 Block 2 Block 8 32-bytes Figure 18-7. Example for dividing large data transfers QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 805 Buffer Port Register 15-8 23-16 31-24 Data Buffer 31-24 23-16 15-8 Figure 18-8. Data swap between buffer data port register and data buffer in big endian mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 806 • The DMA engine stops the transfer and goes to the error state. • The internal data buffer stops accepting incoming data. • The IRQSTAT[DMAE] is set to inform the driver. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 807 ADMA can recognize all kinds of descriptors defined in SD Host Controller Standard and if 'End' flag is detected in the descriptor, ADMA stops after this descriptor is processed. eSDHC supports ADMA1 and ADMA2 with 32-bit addressing. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 808 Kbyte if no set descriptor is ever met. For ADMA2, Tran type descriptor contains both data length and transfer data address. Thus, only a Tran type descriptor can start a data transfer. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 809 Valid=1 indicates this line of descriptor is effective. If Valid=0, generate ADMA error interrupt and stop ADMA. End=1 indicates current descriptor is the ending descriptor. Int=1 generates DMA Interrupt when this descriptor is processed. Figure 18-10. Format of the 32-bit address ADMA1 descriptor table QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 810 Data Address (invisible) Data Length Address Tran, End DMA Interrupt Flags Page Data Transfer Complete SDMA State Machine Block Gap Event Page Data Figure 18-11. Concept and access method of ADMA1 descriptor table QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 811 Data Address (invisible) Address Attribute Address3 Tran, End DMA Interrupt Flags Page Data Transfer Complete SDMA State Machine ADMA Error Page Data Figure 18-13. Concept and access method of ADMA2 descriptor table QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 812 • SD response block: This sub-block monitors the SD CMD line for receiving response and detecting line errors. It sends the command and response status to transfer control for transaction operation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 813 +...+ (last bit) * x CRC[15:0] = Remainder [(M(x) * x ) / G(x)] 18.5.2.3 Tuning block (SDICU) Tuning block is used for SD UHS SDR50, SDR104 and eMMC HS200 modes. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 814 On receiving a command request, the host driver checks the expiration flag. If the expiration flag is set, then the host driver should perform QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 815 This block interfaces with register bus and it contains all the registers. It controls the overall operation of eSDHC and also provides status through various registers. Register accesses is actually on the register bank. See the figure below for the block diagram. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 816 • Software reset for the data part • Software reset for the command part All these signals are fed into this module and stable signals are generated inside the module to reset all other modules. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 817 4,..., or DIV/256. Thus, the highest frequency of the SDHC_CLK is Base, and the next highest is Base/2, while the lowest frequency is Base/4096. The figure below illustrates the sequence for changing the SD clock frequency. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 818 The module detects the CD_B (card detection) as well as the DAT3 signal. The transceiver reports the card insertion state according to the CD_B state, the signal level on the DAT3 signal. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 819 DAT[1] line into the high Z state. eSDHC samples DAT[1] during the interrupt period when the PROCTL[IABG] is set. Refer to SDIO card specification v2.0 for further information about the SDIO card interrupt. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 820 The figure below illustrates the SDIO card interrupt scheme and sequences of software and hardware events that take place during a card interrupt handling procedure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 821 CD pin is always a reference for card detection. Whether the DAT[3] pin or the CD pin is used to detect card insertion, the eSDHC sends an interrupt (if enabled) to inform the host system that a card is inserted. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 822 Before the software disables the host clock, it should ensure that all of the following conditions are met: • No read or write transfer is active • Data and command lines are not active • No interrupts are pending • Internal data buffer is empty QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 823 IRQ Status register and check if any error bits about Command are set if (any error bits are set) report error; write 1 to clear CC bit and all Command Error bits; QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 824 (CMD) only. 18.6.2.1 Card detect The figure below illustrates a flow diagram showing the detection of , SDIO, and SD cards using the eSDHC. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 825 This section is not valid for embedded devices. 18.6.2.2 Reset The host consists of three types of resets: • Hardware reset (card and host) which is driven by POR (power on reset). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 826 Vdd conditions. This means, if the host and card have non-common Vdd ranges, the card will not be able to complete the identification cycle, nor will it be able to send CSD data. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 827 // card is identified as SDIO card } // of if (card is ... send_command(SEND_OP_COND, <voltage range>, <...>); if (RESP_TIMEOUT == wait_for_response(SEND_OP_COND)) { // CMD1 is not accepted, QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 828 (the cards in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bit stream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 829 If the CRC fails, the card should indicate the failure on the DAT line. The transferred data will be discarded and not written, and all further transmitted blocks (in multiple block write mode) will be ignored. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 830 6. Wait for the Transfer Complete interrupt. 7. Check the status bit to see if a write CRC error occurred, or some other error that occurred during the auto12 command sending and response receiving. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 831 (for function 0) or FBR register (for functions 1-7) 3. Set the eSDHC block length register to be the same as the block length set for the card in Step 2. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 832 18.6.3.2 Block read 18.6.3.2.1 Normal read For block reads, the basic unit of data transfer is a block whose maximum size is stored in areas defined by the corresponding card specification. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 833 10. Wait for the Transfer Complete interrupt. 11. Check the status bit to see if a read CRC error occurred, or some other error, occurred during the auto12 command sending and response receiving. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 834 Like the write operation, it is possible to meet the ending block of the transfer when paused. In this case, the eSDHC will ignore the stop at block gap request and treat it as a command read operation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 835 2'b01, so the eSDHC can detect this special setting and be informed that the paused operation has successfully suspended. If the paused transfer is a read operation, the eSDHC stops driving DAT2 and goes to the idle state. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 836 18.6.3.5 Tuning block procedure Tuning block is used for SD UHS SDR50, SDR104 and eMMC HS200 modes. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 837 6. Repeat steps 2-5, if EXTN is not cleared. 7. Check SYSCTL2[SMPCLKSEL], sampling clock select. It's set value indicates tuning procedure success, and clears indicate failure. In case of tuning failure, fixed QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 838 10. Set ESDHCCTL[FAF] 11. Wait for ESDHCCTL[FAF] to be cleared 12. Set SYSCTL[SDCLKEN] 13. Wait for PRSSTAT[SDSTB] to be set NOTE 1. SD clock divisor should be even for DDR mode. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 839 CMD12 (for multi block transfer), apply a reset for data, and re-start the transfer from the corrupted block to recover from the error. 18.6.3.7.3 ADMA transfer error There are three kinds of possible ADMA errors; The System transfer, invalid descriptor, and data-length mismatch errors. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 840 The external cards can inform the host controller by means of some special signals. For the SDIO card, it can be the low level on the DAT[1] line during some special period. The eSDHC only monitors the DAT[1] line and supports the SDIO interrupt. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 841 CMD52 to clear bit EHS at address 0x13 and read after write to confirm EHS bit is cleared; change clock divisor value or configure the system clock feeding into eSDHC to generate the card_clk of the desired value below 25MHz; QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 842 (HS_TIMING is not 0) report the function switch failed and return; change clock divisor value or configure the system clock feeding into eSDHC to generate the card_clk of the desired value below 20MHz; (data transactions like normal peers) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 843 // Make sure the address is 32-bit boundary (lower 2-bit are always '00'). Set higher 32-bit of descriptor for this data transfer initial address; Set [31:16] bits data length (byte unit); QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 844 CMD/DATA DIR and SD_VS pins might be required when interfacing with voltage translator that support DDR, and SDR more than 50 MHz modes. eSDHC SD_VS, or GPIO could be used to control SEL pin of the translator. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 845 CMD line. CMD2 [31:0] stuff bits ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 846 (CSD) on the CMD line. [15:0] stuff bits CMD10 [31:16] RCA SEND_CID Addressed card sends its card- identification (CID) on the CMD line. [15:0] stuff bits Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 847 Normally this command is reserved for the manufacturer. CMD27 adtc [31:0] stuff bits PROGRAM_CSD Programming of the programmable bits of the CSD. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 848 CMD40 [31:0] stuff bits GO_IRQ_STATE Sets the system into interrupt mode in eMMC device. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 849 (to be used for faster multiple block write command) Default value is 1 (one write block). ACMD25 adtc [31:0] stuff bits SECURE_WRITE_MUL Protected Area Access Command: TI_BLOCK Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 850 Writes random number RN1 as challenge1 in AKE process. Refer Security Specification Version 2.00 for more details. ACMD46 adtc [31:0] stuff bits GET_CER_RN2 AKE Command: Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 851 The bits in the pointed byte are set, according to the 1 bit in the Value field. Clear bits The bits in the pointed byte are cleared, according to the 1 bit in the Value field. Write Byte The Value field is written into the pointed byte. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 852 BLKCNT register to its original value, instead of keeping the remaining number of blocks. 18.9.3 Data port access Data port does not support parallel access. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 853 18.9.8 Soft reset for data not allowed when SD clock is disabled Soft reset for data and CMD (SYSCTL[RSTD]/SYSCTL[RSTC]) should not be issued when SD clock is disabled; that is, when SYSCTL[SDCLKEN] is cleared. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 854 TC for Auto CMD12(command with busy). Host Driver needs make sure that card has reached to “trans“ state before issuing any new data command. CMD13(SEND_STATUS) could be sent to check the card status. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 855 The following table lists the SoC signal names and their corresponding FlexTimer module signal names used in this chapter: Table 19-2. LS1012A FlexTimer signals LS1012A signal name FlexTimer module signal FTM_EXTCLK EXTCLK FTMn_CHn Not used FAULTj Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 856 It is possible to chain two FlexTimer controllers to get a bigger 32-bit counter. This is achieved by: • Connecting CH7 output of FlexTimer-B to PHA input of FlexTimer-A. • Tieing PHB input of FlexTimer-A to one. • Programming FlexTimer-A to be in quad-mode. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 857 All of the features common with the TPM have fully backwards compatible register assignments. The FlexTimer can also use code on the same core platform without change to perform the same functions. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 858 • Each channel can be configured for input capture, output compare, or edge-aligned PWM mode • In Input Capture mode: • The capture can occur on rising edges, falling edges or both edges • An input filter can be selected for some channels QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 859 When the chip is in an active mode, the FTM temporarily suspends all counting until the chip returns to normal user operating mode. During Stop mode, all FTM input clocks are stopped, so the FTM is effectively disabled until clocks resume. During Wait mode, the QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 860 For example, if a module instance supports only six channels, references to channel numbers 6 and 7 do not apply for that instance. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 861 7 and polarity control) mode logic input DECAPEN CH7F channel 7 COMBINE3 channel 7 interrupt CPWMS CH7TRIG match trigger CH7IE MS7B:MS7A ELS7B:ELS7A Figure 19-1. FTM block diagram QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 862 This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 863 0000_0000h 19.4.7/871 29D_0044 Channel (n) Status And Control (FTM1_C7SC) 0000_0000h 19.4.6/869 29D_0048 Channel (n) Value (FTM1_C7V) 0000_0000h 19.4.7/871 29D_004C Counter Initial Value (FTM1_CNTIN) 0000_0000h 19.4.8/872 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 864 29E_000C Channel (n) Status And Control (FTM2_C0SC) 0000_0000h 19.4.6/869 29E_0010 Channel (n) Value (FTM2_C0V) 0000_0000h 19.4.7/871 29E_0014 Channel (n) Status And Control (FTM2_C1SC) 0000_0000h 19.4.6/869 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 865 Input Capture Filter Control (FTM2_FILTER) 0000_0000h 19.4.20/ 29E_007C Fault Control (FTM2_FLTCTRL) 0000_0000h 19.4.21/ 29E_0080 Quadrature Decoder Control And Status (FTM2_QDCTRL) 0000_0000h 19.4.22/ 29E_0084 Configuration (FTM2_CONF) 0000_0000h Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 866 SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE CLKS Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 867 This field is write protected. It can be written only when MODE[WPDIS] = 1. Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 868 Initialize the FTM counter, by writing to CNT, before writing to the MOD register to avoid confusion about when the first counter overflow will occur. Address: Base address + 8h offset Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 869 High-true pulses (clear Output on match) Low-true pulses (set Output on match) Center-Aligned High-true pulses (clear Output on match-up) Low-true pulses (set Output on match-up) Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 870 Set by hardware when an event occurs on the channel. CHF is cleared by reading the CSC register while CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 871 These registers contain the captured FTM counter value for the input modes or the match value for the output modes. In Input Capture, Capture Test, and Dual Edge Capture modes, any write to a CnV register is ignored. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 872 FTM counter by writing any value to the CNT register. Address: Base address + 4Ch offset Reserved INIT Reset FTMx_CNTIN field descriptions Field Description 0–15 This field is reserved. Reserved 16–31 Initial Value Of The FTM Counter INIT QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 873 Address: Base address + 50h offset Reset Reset FTMx_STATUS field descriptions Field Description 0–23 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 874 See the register description. No channel event has occurred. A channel event has occurred. Channel 0 Flag CH0F See the register description. No channel event has occurred. A channel event has occurred. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 875 Fault control is disabled for all channels. Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 876 This register configures the PWM synchronization. A synchronization event can perform the synchronized update of MOD, CV, and OUTMASK registers with the value of their write buffer and the FTM counter initialization. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 877 Selects the software trigger as the PWM synchronization trigger. The software trigger happens when a 1 is written to SWSYNC bit. Software trigger is not selected. Software trigger is selected. PWM Synchronization Hardware Trigger 2 TRIG2 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 878 If CNTMIN is one, the selected loading point is when the FTM counter reaches its minimum value (CNTIN register). The minimum loading point is disabled. The minimum loading point is enabled. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 879 The initialization value is 1. Channel 3 Output Initialization Value CH3OI Selects the value that is forced into the channel output when the initialization occurs. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 880 Any write to the OUTMASK register, stores the value in its write buffer. The register is updated with the value of its write buffer according to synchronization. Address: Base address + 60h offset Reset Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 881 CH0OM Defines if the channel output is masked or unmasked. Channel output is not masked. It continues to operate normally. Channel output is masked. It is forced to its inactive state. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 882 DTEN3 Enables the deadtime insertion in the channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 883 The fault control in this pair of channels is enabled. Synchronization Enable For n = 4 SYNCEN2 Enables PWM synchronization of registers C(n)V and C(n+1)V. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 884 Fault Control Enable For n = 2 FAULTEN1 Enables the fault control in channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 885 This field is write protected. It can be written only when MODE[WPDIS] = 1. Channels (n) and (n+1) are independent. Channels (n) and (n+1) are combined. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 886 This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel (n+1) output is the same as the channel (n) output. The channel (n+1) output is the complement of the channel (n) output. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 887 When DTVAL is 2, 2 counts are inserted. This pattern continues up to a possible 63 counts. This field is write protected. It can be written only when MODE[WPDIS] = 1. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 888 Several channels can be selected to generate multiple triggers in one PWM period. See Channel trigger output Initialization trigger. Channels 6 and 7 are not used to generate channel triggers. Address: Base address + 6Ch offset Reserved Reset Reserved Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 889 The generation of the channel trigger is enabled. Channel 2 Trigger Enable CH2TRIG Enables the generation of the channel trigger when the FTM counter is equal to the CnV register. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 890 Channel 5 Polarity POL5 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 891 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 892 FAULTF remains set after the clearing sequence is completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits are cleared individually. No fault condition was detected. A fault condition was detected. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 893 Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when FAULTF bit is cleared. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 894 This field is reserved. Reserved 16–19 Channel 3 Input Filter CH3FVAL Selects the filter value for the channel input. The filter is disabled when the value is zero. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 895 This read-only field is reserved and always has the value 0. 20–23 Fault Input Filter FFVAL Selects the filter value for the fault inputs. The fault filter is disabled when the value is zero. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 896 Fault input is enabled. Fault Input 1 Enable FAULT1EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 897 Fault input is enabled. 19.4.21 Quadrature Decoder Control And Status (FTMx_QDCTRL) This register has the control and status bits for the Quadrature Decoder mode. Address: Base address + 80h offset Reset Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 898 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 899 Enables the global time base signal generation to other FTMs. A global time base signal generation is disabled. A global time base signal generation is enabled. Global Time Base Enable GTBEEN Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 900 Address: Base address + 88h offset Reset Reset FTMx_FLTPOL field descriptions Field Description 0–27 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 901 The fault input polarity is active high. A 1 at the fault input indicates a fault. The fault input polarity is active low. A 0 at the fault input indicates a fault. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 902 FTM counter synchronization is activated by a hardware trigger. HWRSTCNT A hardware trigger does not activate the FTM counter synchronization. A hardware trigger activates the FTM counter synchronization. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 903 CNTIN register is updated with its buffer value by the PWM synchronization. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Trigger Mode HWTRIGMODE Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 904 Inverting is enabled. Pair Channels 2 Inverting Enable INV2EN Inverting is disabled. Inverting is enabled. Pair Channels 1 Inverting Enable INV1EN Inverting is disabled. Inverting is enabled. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 905 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 6 Software Output Control Value CH6OCV Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 906 The channel output is not affected by software output control. The channel output is affected by software output control. Channel 2 Software Output Control Enable CH2OC Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 907 Enables the loading of the MOD, CNTIN, and CV registers with the values of their write buffers. Loading updated values is disabled. Loading updated values is enabled. Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 908 Include the channel in the matching process. 19.5 Functional description The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 909 FTM information for further details. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 910 The FTM counter has these modes of operation: • Up counting • Up-down counting • Quadrature Decoder mode 19.5.3.1 Up counting Up counting is selected when: • QUADEN = 0, and • CPWMS = 0 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 911 FTM counting is up and signed. CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so the FTM counting is up and unsigned. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 912 • Setting CNTIN to be greater than the value of MOD is not recommended as this unusual setting may make the FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 913 The TOF bit is set when the FTM counter changes from MOD to (MOD – 1). If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is, up-down and unsigned counting. See the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 914 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 FTM counter TOF bit set TOF bit Figure 19-8. Example when the FTM counter is free running The FTM counter is also a free running counter when: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 915 FTM counter NUMTOF[4:0] 0x02 TOF counter 0x01 0x02 0x00 0x01 0x02 0x00 0x01 0x02 set TOF bit Figure 19-9. Periodic TOF when NUMTOF = 0x02 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 916 While in , the input capture function works as configured. When a selected edge event occurs, the FTM counter value, which is frozen because of , is captured into the CnV register and the CHnF bit is set. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 917 As long as the new state is stable on the input, the counter continues to increment. When the counter is equal to CHnFVAL[3:0], the state change of the input signal is validated. It is then transmitted as a pulse edge to the edge detector. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 918 The figure below shows an example of input capture with filter enabled and the delay added by each part of the input capture logic. Note that the input signal is delayed only by the synchronizer and edge dector logic if the filter is disabled. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 919 The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 920 CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the channel (n) output is not modified and controlled by FTM. 19.5.6 Edge-Aligned PWM (EPWM) mode The Edge-Aligned mode is selected when: • QUADEN = 0 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 921 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow when the CNTIN register value is loaded into the FTM counter, and it is forced high at the channel (n) match (FTM counter = CnV). See the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 922 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts down until it reaches CNTIN. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 923 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (FTM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up. See the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 924 (n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 925 ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 19-25. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 926 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 Figure 19-28. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 927 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 19-30. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 928 (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 19-33. Channel (n) output if (C(n)V = C(n+1)V = MOD) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 929 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 19-35. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 930 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 19-37. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 931 (n+1) match occurs, that is, FTM counter = C(n+1)V. So, Combine mode allows the generation of asymmetrical PWM signals. 19.5.9 Complementary mode The Complementary mode is selected when: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 932 COMP = 1 Figure 19-41. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1) NOTE The complementary mode is not available in Output Compare mode. 19.5.10 Registers updated from write buffers QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 933 When CnV register is written, independent of FTMEN bit. • CLKS[1:0] ≠ 0:0, and According to the selected mode, that is: • FTMEN = 0 Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 934 If (HWTRIGMODE = 0) then the TRIGn bit is cleared when 0 is written to it or when the trigger n event is detected. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 935 Boundary cycle and loading points and the following figure. If (PWMSYNC = 0) and (REINIT = 1) then SWSYNC bit is cleared when the software trigger event occurs. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 936 For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary cycles are not used as loading points for registers updates. See the register synchronization descriptions in the following sections for details. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 937 = 0). However, it is expected that the MOD register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the MOD register synchronization depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to this flowchart: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 938 If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 939 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 940 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 19-50. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 941 SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the OUTMASK register synchronization depends on SWOM and HWOM bits. See the following flowchart: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 942 ? clear TRIGn bit Figure 19-51. OUTMASK register synchronization flowchart In the case of legacy PWM synchronization, the OUTMASK register synchronization depends on PWMSYNC bit according to the following description. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 943 If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared according to Hardware trigger. An example with a hardware trigger follows. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 944 PWM synchronization (INVC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the INVCTRL register synchronization depends on SWINVC and HWINVC bits. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 945 HWTRIGMODE bit ? clear TRIGn bit Figure 19-55. INVCTRL register synchronization flowchart 19.5.11.9 SWOCTRL register synchronization The SWOCTRL register synchronization updates the SWOCTRL register with its buffer value. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 946 ? bit ? wait hardware trigger n update SWOCTRL with its buffer value update SWOCTRL with its buffer value HWTRIGMODE bit ? clear TRIGn bit Figure 19-56. SWOCTRL register synchronization flowchart QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 947 = 0). However, the FTM counter must be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the FTM counter synchronization depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 948 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 949 Figure 19-61. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 950 NOTE INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 19-62. Channels (n) and (n+1) outputs after the inverting in High-True (ELSnB:ELSnA = 1:0) Combine mode QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 951 The software output control forces the channel output according to software defined values at a specific time in the PWM generation. The software output control is selected when: • QUADEN = 0 • DECAPEN = 0, and • CHnOC = 1 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 952 Software output control forces the following values on channels (n) and (n+1) when the COMP bit is one. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 953 If POL(n) = 1, POL(n+1) = 1, and the deadtime is enabled, then when the channel (n) match (FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 954 • The deadtime feature must be used only in Complementary mode. • The deadtime feature is not available in Output Compare mode. 19.5.14.1 Deadtime insertion corner cases If (PS[2:0] is cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1): QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 955 Figure 19-68. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty cycle QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 956 Table 19-14. Output mask result for channel (n) before the polarity control CHnOM Output Mask Input Output Mask Result inactive state inactive state active state active state inactive state inactive state active state QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 957 FAULTFn* control detector Fault filter (5-bit counter) system clock * where n = 3, 2, 1, 0 Figure 19-70. Fault input n control block diagram QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 958 If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 959 If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then the channels output disabled by fault control is again enabled when the FAULTF bit is cleared and a new PWM cycle begins. See the following figure. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 960 • If POLn = 1, the channel (n) output polarity is low, so the logical zero is the active state and the logical one is the inactive state. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 961 See the description of the CLKS field in the Status and Control register. 19.5.19 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 962 = 0, 1, 2, 3, 4, or 5, then the FTM generates a trigger when the channel (j) match occurs (FTM counter = C(j)V). The channel trigger output provides a trigger signal which has one FTM clock period width and is used for on-chip modules. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 963 Figure 19-75. Channel match trigger 19.5.21 Initialization trigger If INITTRIGEN = 1, then the FTM generates a trigger when the FTM counter is updated with the CNTIN register value in the following cases. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 964 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 FTM counter write to CNT initialization trigger Figure 19-77. Initialization trigger is generated when there is a write to CNT register QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 965 CHnF bits are set. Therefore, the FTM counter is updated with its next value according to its configuration. Its next value depends on CNTIN, MOD, and the written value to FTM counter. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 966 If DMA = 1, the CHnF bit is cleared either by channel DMA transfer done or reading CnSC while CHnF is set and then writing a zero to CHnF bit according to CHnIE bit. See the following table. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 967 (n) interrupt is generated (if CH(n)IE = 1). If the selected edge by channel (n+1) bits is detected at channel (n) input and (CH(n)F = 1), then CH(n+1)F bit is set and the channel (n+1) interrupt is generated (if CH(n+1)IE = 1). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 968 C(n)V and C(n+1)V registers. Similarly, when the CH(n+1)F bit is set, both edges were captured and the captured values are ready for reading in the C(n)V and C(n+1)V registers. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 969 DECAP bit is cleared when the second edge of this pulse is detected, that is, the edge selected by ELS(n+1)B:ELS(n+1)A bits. Both DECAP and CH(n+1)F bits indicate when two edges of the pulse were captured and the C(n)V and C(n+1)V registers are ready for reading. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 970 ELS(n +1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the pulse were captured and the C(n)V and C(n+1)V registers are ready for reading. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 971 If both channels (n) and (n+1) are configured to capture falling edges (ELS(n)B:ELS(n)A = 1:0 and ELS(n+1)B:ELS(n+1)A = 1:0), then the period between two consecutive falling edges is measured. The period measurement can be made in One-Shot Capture mode Continuous Capture mode. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 972 Dual Edge Capture mode, so it remains set. While the DECAP bit is set the configured measurements are made. The CH(n)F bit is set when the first rising edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit is set QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 973 Thus, the channel (n) is configured to capture the FTM counter value when there is a rising edge at channel (n) input signal, and channel (n+1) to capture the FTM counter value when there is a falling edge at channel (n) input signal. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 974 The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder mode uses the input signals phase A and B to control the FTM counter increment and decrement. The following figure shows the quadrature decoder block diagram. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 975 An edge at phase A must not occur together an edge at phase B and vice-versa. The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects the polarity of the phase B input. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 976 • there is a rising edge at phase B signal and phase A signal is at logic zero; • there is a rising edge at phase A signal and phase B signal is at logic one. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 977 FTM counter changes from CNTIN to MOD, TOF bit is set and TOFDIR bit is cleared. TOF bit indicates the FTM counter overflow occurred. TOFDIR indicates the counting was down when the FTM counter overflow occurred. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 978 B FTM counter CNTIN 0x0000 Time Figure 19-92. Motor position jittering in a mid count value The following figure shows motor jittering produced by the phase B and A pulses respectively: QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 979 When the FTM counter wraps from MOD value to CNTIN Always value At the channel (j) match (FTM counter = C(j)V) When CHjSEL = 1 The following figure shows some examples of enabled loading points. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 980 • If ELSjB and ELSjA bits are different from zero, then the channel (j) output signal is generated according to the configured output mode. If ELSjB and ELSjA bits are zero, QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 981 Note that these configurations are chip-dependent and implemented outside of the FTM modules. See the chip-specific FTM information for the chip's specific implementation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 982 • the channels are in input capture mode, see Input Capture mode; • the channels outputs are zero; • the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0:0) (See the table in the description of CnSC register). QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 983 CNT register (item 3). In this case, use the software output control (Software output control) or the initialization (Initialization) to update the channel output to the selected value (item QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 984 The fault interrupt is generated when (FAULTIE = 1) and (FAULTF = 1). 19.8 Initialization Procedure The following initialization procedure is recommended to configure the FlexTimer operation. This procedure can also be used to do a new configuration of the FlexTimer operation. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 985 Synchronization for write buffers (because the writes to registers with write buffer are done using CLKS[1:0] = 2’b00): SWWRBUF = 0 and CNTINC = • SW Synchronization for counter reset (always): SWRSTCNT = 1. • Enhanced synchronization (always): SYNCMODE = 1 QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 986 • Generate the Software Trigger Write to SYNC (SWSYNC = 1, TRIG2 = 0, TRIG1 = 0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0, CNTMIN = 0) QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 987 • Reserved port: GPIO2[8] 20.2 GPIO overview This chapter describes the general-purpose I/O (GPIO) module, including signal descriptions, register settings and interrupt capabilities. This figure shows the block diagram for the GPIO module. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 988 • All signals are high-impedance during reset • Open-drain capability on all ports • All ports can optionally generate an interrupt upon changing their state • Ports may be multiplexed with other functional signals QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 989 GPIO1 base address: 230_0000h GPIO2 base address: 231_0000h Offset Register Width Access Reset value (In bits) GPIO direction register (GPDIR) 0000_0000h GPIO open drain register (GPODR) 0000_0000h Table continues on the next page... QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 990 0000_0000h 20.5.2 GPIO direction register (GPDIR) 20.5.2.1 Offset Register Offset GPDIR 20.5.2.2 Function The GPIO direction register (GPDIR) defines the direction of the individual ports. 20.5.2.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 991 20.5.3 GPIO open drain register (GPODR) 20.5.3.1 Offset Register Offset GPODR 20.5.3.2 Function The GPIO open drain register (GPODR) defines the way individual ports drive their output. 20.5.3.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 992 20.5.4 GPIO data register (GPDAT) 20.5.4.1 Offset Register Offset GPDAT 20.5.4.2 Function The GPIO data register (GPDAT) carries the data in/out for the individual ports. 20.5.4.3 Diagram Bits Reset Bits Reset QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 993 GPIMR. In these implementations, a GPIER bit can be set even though the associated interrupt is masked. See The "GPIO module as implemented on the chip" section for more information. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 994 When a masked interrupt request occurs, the corresponding GPIER bit is set, regardless of the GPIMR state. When one or more non-masked interrupt events occur, the GPIO module issues an interrupt to the interrupt controller. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 995 20.5.7.2 Function The GPIO interrupt control register (GPICR) determines whether the corresponding port line asserts an interrupt request upon either a high-to-low change or any change on the state of the signal. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 996 Edge detection mode. The corresponding port line asserts an interrupt request according to the following: 00000000000000000000000000000000b - Any change on the state of the port generates an interrupt request. 00000000000000000000000000000001b - High-to-low change on the port generates an interrupt request. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 997 The following table lists the SoC signal names and their corresponding I C module signal names used in this chapter: Table 21-2. LS1012A I C signals LS1012A signal name C module signal IICn_SCL IICn_SDA QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 998 C) bus module implemented on this chip and presents the following topics: • Introduction to I • External signal descriptions • Memory map and register definition • Functional description • Initialization/application information QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 999 • Does not require an external address decoder 21.3.3 Module block diagram The following figure shows a block diagram of the I C module. QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 NXP Semiconductors...
Page 1000 • Up to 100 kbps in Standard Mode • Up to 400 kbps in Fast Mode 1. Compliant with I C 2.0 standard with the exception that HS (high speed) mode is not supported QorIQ LS1012A Reference Manual, Rev. 1, 01/2018 1000 NXP Semiconductors...

NXP Semiconductors QorIQ LS1012A Reference Manual

Section Number Title Page

Ch Status Register (Status_Register)/Read Channel Qos Value Override Register

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Summary of Contents for NXP Semiconductors QorIQ LS1012A

Page 89: Table Of Contents

Page 302: Offset

Page 303: Fields

Page 304: Fields

Page 317: Ch Status Register (Status_Register)

Page 319: Imprecise Error Register (Imprecise_Error_Register)

Page 336: Snoop Control Registers (Snoop_Control_Register_S0)

Page 343: Register_S0)

Page 346: Max Ot Registers (Max_Ot_Register_S0)

Page 419: Diagram

Page 420: Offset

Page 441: Diagram

Page 442: Offset

Page 482: Fields

Page 487: Diagram

NXP Semiconductors QorIQ LS1012A Reference Manual

Section Number Title Page

Ch Status Register (Status_Register)/Read Channel Qos Value Override Register

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Summary of Contents for NXP Semiconductors QorIQ LS1012A

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