NXP Semiconductors MCF5253 Manuals

Manuals and User Guides for NXP Semiconductors MCF5253. We have 2 NXP Semiconductors MCF5253 manuals available for free PDF download: Reference Manual, Quick Start Manual

NXP Semiconductors MCF5253 Reference Manual (648 pages)

Brand: NXP Semiconductors | Category: Computer Hardware | Size: 9 MB

Table of Contents
3
MCF5253 Reference Manual
26
Chapter 1 MCF5253 Introduction

33
- MCF5253 Overview
  33
- MCF5253 Feature Introduction
  33
- MCF5253 Block Diagram
  34
- MCF5253 Feature Details
  36
- MCF5253 Functional Overview
  39
- Coldfire CF2 Core
  39
- DMA Controller
  39
- Enhanced Multiply and Accumulate Module (Emac)
  39
- Instruction Cache
  40
- Internal 128-Kbyte SRAM
  40
- DRAM Controller
  40
- System Interface
  40
- External Bus Interface
  40
- USB 2.0 High-Speed On-The-Go
  40
- ATA Controller
  41
- Two Controller Area Network (CAN) 2.0B Communication Unit
  41
- Real-Time Clock
  41
- Serial Audio Interfaces
  41
- IEC958 Digital Audio Interfaces
  41
- Audio Bus
  41
- CD-ROM Encoder/Decoder
  42
- Three UART Modules
  42
- Queued Serial Peripheral Interface QSPI
  42
- Timer Module
  43
- IDE Interface
  43
- Analog/Digital Converter (ADC)
  43
- Flash Memory Card Interface
  43
- I 2 C Module
  43
- Chip-Selects
  43
- GPIO Interface
  44
- Interrupt Controller
  44
- Jtag
  44
- System Debug Interface
  44
- System Oscillator and PLL
  44
- Sleep and Wake-Up Modes
  45
- Bootloader
  45
- Internal Voltage Regulator
  45
Chapter 2 Contents

47
Signal Description

47
- Overview
  47
- Gpio
  51
- MCF5253 Bus Signals
  51
- Address Bus
  51
- Read-Write Control
  52
- Output Enable
  52
- Data Bus
  52
- Transfer Acknowledge
  52
- SDRAM Controller Signals
  52
- Chip Selects
  53
- ISA Bus
  53
- Bus Buffer Signals
  53
- I2C Module Signals
  53
- Serial Module Signals
  54
- Timer Module Signals
  54
- Serial Audio Interface Signals
  54
- Digital Audio Interface Signals
  55
- Subcode Interface
  56
- Analog to Digital Converter (ADC)
  56
- Secure Digital / Memory Stick Card Interface
  56
- Queued Serial Peripheral Interface (QSPI)
  57
- ATA Interface
  57
- Two Controller Area Network (CAN) Communication Modules
  57
- USB Controller
  58
- USB PHY Interface Including Oscillator
  58
- Real-Time Clock
  58
- Crystal Trim
  58
- Clock out
  58
- Debug and Test Signals
  58
- Test Mode
  59
- High Impedance
  59
- Processor Clock Output
  59
- Debug Data
  59
- Processor Status
  59
- BDM/JTAG Signals
  60
- Clock and Reset Signals
  60
- Reset in
  60
- System Bus Input
  60
- Wake-Up Signal
  60
- On-Chip Linear Regulator
  61
Chapter 3 Coldfire Core

63
Chapter 4 Phase-Locked Loop and Clock Dividers

81
- PLL Features
  81
- PLL Memory Map and Register Definitions
  82
- PLL Operation
  85
- PLL Lock-In Time
  85
- PLL Electrical Limits
  85
- Dynamic Clock Switching
  86
- Audio Clock Generation
  86
- Reduced Power Mode
  87
- Sleep / Wake-Up Mode
  87
- Enter Sleep Mode
  88
- Exit Sleep Mode
  88
- Selecting Audio_Clock Input
  88
- Recommended Settings
  88
Chapter 5 Instruction Cache

89
Chapter 6 Static RAM (SRAM)

99
- SRAM Features
  99
- SRAM Operation
  99
- SRAM Memory Map and Register Definitions
  99
- SRAM Base Address Register
  99
- SRAM Initialization
  102
- SRAM Initialization Code
  102
- Power Management
  102
Chapter 7 Synchronous DRAM Controller Module

105
- SDRAM Features
  105
- Block Diagram
  105
- Synchronous Operation
  106
- DRAM Controller Signals in Synchronous Mode
  107
- SDRAM Memory Map and Register Definitions
  107
- DRAM Controller Registers
  108
- DRAM Control Register (DCR) (Synchronous Mode)
  108
- DRAM Address and Control (DACR0) (Synchronous Mode)
  109
- DRAM Controller Mask Registers (DMR0)
  111
- General Synchronous Operation Guidelines
  112
- Address Multiplexing
  112
- Interfacing Example
  114
- Burst
  114
- Continuous
  116
- Continuous Page Mode
  116
- Auto-Refresh Operation
  118
- Self-Refresh Operation
  119
- Initialization Sequence
  120
- Mode Register Settings
  120
- SDRAM Example
  121
- SDRAM Interface Configuration
  122
- DCR Initialization
  122
- DACR Initialization
  123
- DMR Initialization
  124
- Mode Register Initialization
  125
- Initialization Code
  126
Chapter 8 Bus Operation

129
- Bus Features
  129
- Bus and Control Signals
  129
- Address Bus
  130
- Read/Write Control
  130
- Transfer Acknowledge (TA)
  130
- Data Bus
  130
- Chip Selects
  131
- Output Enable
  131
- Clock and Reset Signals
  131
- Reset in
  132
- System Bus Clock Output
  132
- Bus Characteristics
  132
- Data Transfer Operation
  132
- Bus Cycle Execution
  133
- Read Cycle
  134
- Write Cycle
  136
- Back-To-Back Bus Cycles
  137
- Burst Cycles
  138
- Line Transfers
  138
- Line Read Bus Cycles
  138
- Misaligned Operands
  141
- Reset Operation
  142
- Software Watchdog Reset
  143
Chapter 9 System Integration Module (SIM)

145
- SIM Overview
  145
- SIM Features
  145
- SIM Memory Map and Register Definitions
  145
- SIM Register Memory Map
  146
- SIM Module Programming Registers
  147
- Module Base Address Registers
  147
- Device ID Register
  150
- Interrupt Interface Registers
  150
- Primary Interrupt Controller Registers
  151
- Interrupt Mask Register
  154
- Interrupt Pending Register
  154
- Secondary Interrupt Controller Registers
  155
- Interrupt Level Selection
  156
- Interrupt Vector Generation Register
  156
- Spurious Vector Register
  157
- Secondary Interrupt Sources
  157
- Software Interrupts
  160
- Interrupt Monitor
  160
- System Protection and Reset Status Registers
  161
- Reset Status Register
  161
- Software Watchdog Timer
  161
- System Protection Control Register
  163
- Software Watchdog Interrupt Vector Register
  164
- Software Watchdog Service Register
  165
- CPU HALT Instruction
  165
- MCF5253 Bus Arbitration Control Registers
  165
- Default Bus Master Park Register
  165
- Internal Arbitration Operation
  166
- PARK Register Bit Configuration
  167
- General Purpose I/Os
  168
- General Purpose Inputs
  169
- General Purpose Input Interrupts
  170
- General Purpose Outputs
  171
- Multiplexed Pin Configuration
  173
Chapter 10 Chip Select Module

177
- Chip Select Features
  177
- Chip Select Signals
  177
- Cs0/Cs4
  177
- Cs1/Qspi_Cs3/Gpio28
  178
- CS2 - IDE_DIOR/GPIO31 and IDE_DIOW/GPIO32
  178
- Cs3
  178
- Output Enable Signal OE
  178
- Buffer Enable - BUFENB1 and BUFENB2 Signals
  178
- Bus Termination Signal - IDE_IORDY
  178
- Chip Select Operation
  179
- General-Purpose Chip Select Operation
  179
- Port Sizing
  179
- Global Chip-Select Operation
  180
- Chip Select Memory Map and Register Definitions
  180
- Chip Select Register Memory Map
  180
- Chip Select Module Registers
  181
- Chip Select Address Register
  181
- Chip Select Mask Register
  182
- Chip Select Control Register
  184
- Code Example
  186
Chapter 11 General Purpose Timer Modules

187
- Timer Module Overview
  187
- Timer Features
  187
- Block Diagram
  187
- Timer Signal Output
  188
- Timer Operation
  188
- Selecting the Prescaler
  188
- Configuring the Timer for Reference Compare
  188
- Configuring the Timer for Output Mode (TIMER0)
  189
- General-Purpose Timer Memory Map and Register Definitions
  189
- Timer Mode Registers (TMR0, TMR1)
  189
- Timer Reference Registers (TRR0, TRR1)
  190
- Timer Counters (TCN0, TCN1)
  191
- Timer Event Registers (TER0, TER1)
  191
- Timer Initialization Example Code
  192
- Timer0 (Timer Mode Register)
  192
- Timer0 (Timer Reference Register0)
  192
Chapter 12 Analog to Digital Converter (ADC)

193
- Overview
  193
- Block Diagram
  193
- External Signal Description
  193
- ADC Memory Map and Register Definitions
  194
- AD Configuration Register (Adconfig)
  194
- AD Value Register (Advalue)
  195
- Functional Description
  196
- Recommendations to Set-Up of ADC and External Components
  196
Chapter 13 IDE and Flash Media Interface

199
Chapter 14 DMA Controller

229
- DMA Features
  229
- DMA Signal Description
  229
- DMA Request
  230
- DMA Module Overview
  231
- DMA Memory Map and Register Definitions
  232
- REQUEST Source Selection
  232
- Source Address Register
  233
- Destination Address Register
  234
- Byte Count Register
  235
- DMA Control Register
  236
- DMA Status Register
  239
- DMA Interrupt Vector Register
  240
- Transfer Request Generation
  241
- Cycle-Steal Mode
  241
- Continuous Mode
  241
- Data Transfer Modes
  241
- Dual-Address Transaction
  241
- Dual-Address Read
  241
- Dual-Address Write
  242
- DMA Transfer Functional Description
  242
- Channel Initialization and Startup
  242
- Channel Prioritization
  243
- Programming the DMA
  243
- Data Transfer
  244
- Periphery Request Operation
  244
- Auto Alignment
  244
- Bandwidth Control
  244
- Channel Termination
  245
- Error Conditions
  245
- Interrupts
  245
Chapter 15 UART Modules

247
- UART Module Features
  247
- Serial Communication Channel
  248
- Baud-Rate Generator/Timer
  248
- Interrupt Control Logic
  248
- UART Module Signal Definitions
  249
- Transmitter Serial Data Output
  249
- Receiver Serial Data Input
  249
- Request-To-Send
  250
- Clear-To-Send
  250
- Operation
  250
- Baud-Rate Generator/Timer
  251
- Calculating Baud Rates
  251
- Transmitter and Receiver Operating Modes
  251
- Transmitter
  252
- Receiver
  254
- Receiver FIFO
  255
- Looping Modes
  256
- Automatic Echo Mode
  256
- Local Loopback Mode
  257
- Remote Loopback Mode
  257
- Multidrop Mode
  258
- Bus Operation
  259
- Read Cycles
  259
- Write Cycles
  259
- Interrupt Acknowledge Cycles
  259
- UART Memory Map and Register Definitions
  259
- Mode Register 1 (Umr1N)
  260
- Mode Register 2 (Umr2N)
  262
- Status Registers (Usrn)
  263
- Clock-Select Registers (Uscrn)
  265
- Command Registers (Ucrn)
  266
- Miscellaneous Commands
  266
- Reset Mode Register Pointer
  266
- Reset Receiver
  266
- Reset Transmitter
  267
- Reset Error Status
  267
- Reset Break-Change Interrupt
  267
- Start Break
  267
- Stop Break
  267
- Transmitter Commands
  267
- No Action Taken
  267
- Transmitter Enable
  268
- Transmitter Disable
  268
- Do Not Use
  268
- Receiver Commands
  268
- No Action Taken
  268
- Receiver Enable
  268
- Receiver Disable
  268
- Receiver Buffer Registers (Ubrn)
  269
- Transmitter Buffer Registers (Utbn)
  269
- Input Port Change Registers (Uipcrn)
  270
- Auxiliary Control Registers (Uacrn)
  270
- Interrupt Status Registers (Uisrn)
  271
- Interrupt Mask Registers (Uimrn)
  272
- Baud Rate Generator (MSB) Register (Ubg1N)
  273
- Baud Rate Generator (LSB) Register (Ubg2N)
  273
- Interrupt Vector Registers (Uivrn)
  273
- Input Port Registers (Uipn)
  273
- Output Port Data Registers (Uop1N)
  274
- 15.4.17 Programming
  275
- 15.4.17.1 UART Module Initialization
  275
- 15.4.17.2 I/O Driver Example
  275
- 15.4.17.3 Interrupt Handling
  275
- UART Module Initialization Sequence
  276
Chapter 16 Queued Serial Peripheral Interface (QSPI) Module

283
- Features
  283
- QSPI Module Overview
  283
- Interface and Pins
  283
- Internal Bus Interface
  284
- Operation
  284
- Qspi Ram
  285
- Transmit RAM
  287
- Receive RAM
  287
- Command RAM
  287
- Baud Rate Selection
  288
- Transfer Delays
  288
- Transfer Length
  289
- Data Transfer
  289
- QSPI Memory Map and Register Definitions
  290
- QSPI Mode Register (QMR)
  290
- QSPI Delay Register (QDLYR)
  292
- QSPI Wrap Register (QWR)
  292
- QSPI Interrupt Register (QIR)
  293
- QSPI Address Register (QAR)
  294
- QSPI Data Register (QDR)
  294
- Command RAM Registers (QCR0-QCR15)
  295
- Programming Example
  296
Chapter 17 Audio Interface Module (AIM)

299
Chapter 18 I 2 C Modules

345
- I2C Interface Features
  345
- I 2 C Overview
  346
- I 2 C System Configuration
  347
- I 2 C Protocol
  347
- START Signal
  348
- Slave Address Transmission
  348
- Data Transfer
  348
- Repeated START Signal
  349
- STOP Signal
  349
- Arbitration Procedure
  349
- Clock Synchronization
  349
- Handshaking
  350
- Clock Stretching
  350
- I 2 C Memory Map and Register Descriptions
  350
- I 2 C Address Registers (MADR)
  350
- I 2 C Frequency Divider Registers (MFDR)
  350
- I 2 C Control Registers (MBCR)
  351
- I 2 C Status Registers (MBSR)
  354
- I 2 C Data I/O Registers (MBDR)
  356
- I 2 C Programming Examples
  356
- Initialization Sequence
  356
- Generation of START
  357
- Post-Transfer Software Response
  358
- Generation of STOP
  358
- Generation of Repeated START
  359
- Slave Mode
  359
- Arbitration Lost
  360
Chapter 19 Boot ROM

363
- Overview
  363
- Boot Modes
  363
- Boot ROM Operation
  364
- Initialization
  364
- Boot ROM Memory Map
  364
- Internal SRAM Usage
  364
- Boot Type Detection
  365
- Serial Boot Data Format
  366
- Command Encoding/Size Encoding
  366
- Supported Commands
  367
- IDE Boot Data Format
  367
- Boot Modes
  367
- Boot from I C / SPI - Master Mode
  367
- Boot from I 2 C - Slave Mode
  368
- Boot from UART
  368
- UART Protocol
  368
- Boot from IDE Device
  368
- Creating Appropriate Boot Record Files
  369
Chapter 20 Background Debug Mode (BDM) Interface

371
- Debug Support Signals
  371
- Breakpoint (BKPT)
  372
- Debug Data (DDATA[3:0])
  372
- Development Serial Clock (DSCLK)
  372
- Development Serial Input (DSI)
  372
- Development Serial Output (DSO)
  372
- Processor Status (PST[3:0])
  372
- Processor Status Clock (PSTCLK)
  373
- Real-Time Trace Support
  373
- Processor Status Signal Encoding
  374
- Continue Execution (PST = $0)
  374
- Begin Execution of an Instruction (PST = $1)
  374
- Entry into User Mode (PST = $3)
  374
- Begin Execution of PULSE or WDDATA Instructions (PST = $4)
  374
- Begin Execution of Taken Branch (PST = $5)
  375
- Begin Execution of RTE Instruction (PST = $7)
  376
- Begin Data Transfer (PST = $8-$B)
  376
- Exception Processing (PST = $C)
  376
- Emulator Mode Exception Processing (PST = $D)
  376
- Processor Stopped (PST = $E)
  376
- Processor Halted (PST = $F)
  376
- Background-Debug Mode (BDM)
  376
- CPU Halt
  377
- BDM Serial Interface
  378
- Receive Packet Format
  379
- Transmit Packet Format
  379
- BDM Command Set
  380
- BDM Command Set Summary
  380
- Command Sequence Diagram
  382
- Command Set Descriptions
  383
- Read Address/Data Register (RAREG/RDREG)
  383
- Write Address/Data Register (WAREG and WDREG)
  384
- Read Memory Location (READ)
  384
- Write Memory Location (WRITE)
  386
- Dump Memory Block (DUMP)
  387
- Fill Memory Block (FILL)
  389
- Resume Execution (GO)
  391
- No Operation (NOP)
  391
- Read Control Register (RCREG)
  392
- Write Control Register (WCREG)
  393
- Read Debug Module Register (RDMREG)
  394
- Write Debug Module Register (WDMREG)
  394
- 20.3.4.1.13 Unassigned Opcodes
  395
- BDM Accesses of the Emac Registers
  395
- Real-Time Debug Support
  396
- Theory of Operation
  397
- Emulator Mode
  398
- Debug Module Hardware
  399
- Reuse of Debug Module Hardware (Rev. A)
  399
- Debug Module Memory Map and Register Definitions
  399
- Address Breakpoint Registers
  400
- Address Attribute Trigger Register
  401
- Program Counter Breakpoint Register (PBR, PBMR)
  402
- Data Breakpoint Registers (DBR, DBMR)
  403
- Trigger Definition Register (TDR)
  405
- Configuration/Status Register (CSR)
  406
- BDM Address Attribute Register (BAAR)
  409
- Concurrent BDM and Processor Operation
  409
- Freescale-Recommended BDM Pinout
  410
Chapter 21 IEEE 1149.1 Test Access Port (JTAG)

411
- Features
  411
- Block Diagram
  411
- JTAG Signal Descriptions
  412
- Test Clock (TCK)
  413
- Test Reset/Development Serial Clock (TRST/DSCLK)
  413
- Test Mode Select/ Breakpoint (TMS/BKPT)
  413
- Test Data Input/Development Serial Input (TDI/DSI)
  414
- Test Data Output/Development Serial Output (TDO/DSO)
  414
- TAP Controller
  414
- Idcode
  416
- JTAG Register Definitions
  416
- SAMPLE/PRELOAD Instruction
  417
- CLAMP Instruction
  417
- HIGHZ Instruction
  417
- BYPASS Instruction
  418
- ID Code Register
  418
- JTAG Boundary Scan Register
  419
- JTAG Bypass Register
  419
- Restrictions
  419
- Disabling IEEE 1149.1A Standard Operation
  419
- Obtaining the IEEE 1149.1A Standard
  420
Chapter 22 USB, ATA DMA, and Clock Integration Module

421
- Introduction
  421
- Memory Map and Register Definitions
  421
- Miscellaneous Configuration Register (MISCCR)
  421
- ATA DMA Address Register (ATA_DADDR)
  423
- ATA DMA Count Register (ATA_DCOUNT)
  423
- RTC Time Register (RTC_TIME)
  423
- Usb/Flexcan Clock Register (USBCANCLK)
  424
- Functional Description
  424
- ATA/USB Cache Memory
  424
- Endianness Issues
  425
- DMA Transfer between ATA and Cache RAM
  425
Chapter 23 Advanced Technology Attachment Controller (ATA)

427
- Features
  427
- Block Diagram
  427
- Overview
  428
- Modes of Operation
  429
- External Signal Description
  430
- Detailed Signal Descriptions
  430
- ATA_RST (Out)
  430
- ATA_DIOR (Out)
  430
- ATA_DIOW (Out)
  430
- ATA_DMARQ (In)
  430
- ATA_DMACK (Out)
  430
- ATA_INTRQ (In)
  430
- ATA_IORDY (In)
  430
- Timing Parameters
  432
  - Timing on ATA Bus
    432
  - PIO Mode Timing
    433
  - Timing in Multiword DMA Mode
    434
- UDMA in Timing Diagrams
  436
- UDMA out Timing Diagrams
  438
- Memory Map and Register Definitions
  440
- Memory Map
  441
- Register Descriptions
  444
- Endianness
  444
- Timing Registers
  445
  - TIME_1 Register
    446
  - TIME_AX Register
    447
  - TIME_M Register
    448
  - TIME_K Register
    449
- 23.5.2.2.17 TIME_ZAH Register
  450
- 23.5.2.2.18 TIME_MLIX Register
  450
- 23.5.2.2.19 TIME_DVH Register
  450
- TIME_DZFS Register
  451
- 23.5.2.2.24 TIME_CYC Register
  452
- FIFO Data Registers
  452
- Fifo_Data Register in 16-Bit Mode
  452
- Fifo_Data Register in 32-Bit Mode
  452
- FIFO_FILL Register
  453
- ATA_CONTROL Register
  453
- Interrupt Registers
  454
- Interrupt_Enable Register
  456
- Interrupt_Clear Register
  457
- FIFO Alarm Register
  457
- Functional Description
  458
- Drive Registers Connected to ATA Bus
  458
- Resetting ATA Bus
  459
- Programming ATA Bus Timing and Iordy_En
  459
- Access to ATA Bus in PIO Mode
  459
- Using DMA Mode to Receive Data from ATA Bus
  460
- Using DMA Mode to Transmit Data to ATA Bus
  461
  - Features
    463
  - Block Diagram
    464
  - Modes of Operation
    465
  - System Clock
    466
  - Module Identification Registers
    467
  - General Hardware Parameters (HWGENERAL) Register
    469
  - Host Hardware Parameters (HWHOST) Register
    470
  - Transmit Buffer Hardware Parameters (HWTXBUF) Register
    471
  - Receive Buffer Hardware Parameters (HWRXBUF) Register
    472
  - Capability Registers
    473
  - Host Controller Structural Parameters (HCSPARAMS)
    474
  - Device Controller Interface Version (DCIVERSION)
    476
  - Operational Registers
    477
  - USB Status Register (USBSTS)
    480
  - USB Interrupt Enable Register (USBINTR)
    482
  - Frame Index Register (FRINDEX)
    483
  - Control Data Structure Segment Register (CTRLDSSEGMENT)
    485
  - Device Address Register (DEVICEADDR), Non-EHCI
    486
  - Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI
    487
  - Master Interface Data Burst Size Register (Burstsize)—Non-EHCI
    488
  - Transmit FIFO Tuning Controls Register (Txfilltuning)—Non-EHCI
    489
  - Configure Flag Register (CONFIGFLAG)
    491
  - On-The-Go Status and Control (OTGSC), Non-EHCI
    496
  - USB Mode Register (Usbmode)—Non-EHCI
    499
  - Endpoint Setup Status Register (Endptsetupstat)—Non-EHCI
    500
  - Endpoint Initialization Register (Endptprime)—Non-EHCI
    501
  - Endpoint Flush Register (ENDPTFLUSH), Non-EHCI
    502
  - Endpoint Status Register (ENDPTSTATUS), Non-EHCI
    503
  - Endpoint Complete Register (ENDPTCOMPLETE), Non-EHCI
    504
  - Endpoint Control Register N (Endptctrln), Non-EHCI
    506
  - Functional Description
    507
  - FIFO RAM Controller
    508
  - Periodic Frame List
    509
  - Asynchronous List Queue Head Pointer
    510
  - Isochronous (High-Speed) Transfer Descriptor (Itd)
    511
  - Itd Transaction Status and Control List
    512
  - Itd Buffer Page Pointer List (Plus)
    513
  - Split Transaction Isochronous Transfer Descriptor (Sitd)
    514
  - Sitd Endpoint Capabilities/Characteristics
    515
  - Sitd Transfer State
    516
  - Sitd Buffer Pointer List (Plus)
    517
  - Sitd Back Link Pointer
    518
  - Next Qtd Pointer
    519
  - Qtd Token
    520
  - Qtd Buffer Page Pointer List
    523
  - Queue Head Horizontal Link Pointer
    524
  - Transfer Overlay
    526
  - Periodic Frame Span Traversal Node (FSTN)
    527
  - FTSN Normal Path Pointer
    528
  - Host Controller Initialization
    529
  - Power Port
    530
  - Port Suspend/Resume
    531
  - Schedule Traversal Rules
    532
  - Periodic Schedule Frame Boundaries Vs. Bus Frame Boundaries
    534
  - Periodic Schedule
    536
  - Managing Isochronous Transfers Using Itds
    537
  - Software Operational Model for Itds
    539
  - Periodic Scheduling Threshold
    540
  - Asynchronous Schedule
    541
  - Adding Queue Heads to Asynchronous Schedule
    542
  - Removing Queue Heads from Asynchronous Schedule
    543
  - Empty Asynchronous Schedule Detection
    545
  - Asynchronous Schedule Traversal: Start Event
    546
  - Buffer Pointer List Use for Data Streaming with Qtds
    547
  - Adding Interrupt Queue Heads to the Periodic Schedule
    549
  - Ping Control
    550
  - Split Transactions
    551
  - Asynchronous—Do-Start-Split
    552
  - Split Transaction Interrupt
    553
  - Host Controller Operational Model for Fstns
    556
  - Software Operational Model for Fstns
    558
  - Tracking Split Transaction Progress for Interrupt Transfers
    559
  - Periodic Interrupt—Do-Start-Split
    560
  - Periodic Interrupt—Do-Complete-Split
    561
  - Managing the Qh[Frametag] Field
    564
  - Rebalancing the Periodic Schedule
    565
  - Split Transaction Scheduling Mechanisms for Isochronous
    566
  - Tracking Split Transaction Progress for Isochronous Transfers
    569
  - Split Transaction Execution State Machine for Isochronous
    571
  - Periodic Isochronous—Do Complete Split
    573
  - Complete-Split for Scheduling Boundary Cases 2A, 2B
    576
  - Split Transaction for Isochronous—Processing Examples
    577
  - Port Test Modes
    578
  - Interrupts
    579
  - Transfer/Transaction Based Interrupts
    580
  - Data Buffer Error
    581
  - USB Interrupt (Interrupt on Completion (IOC))
    582
  - Host System Error
    583
  - Endpoint Queue Head
    584
  - Endpoint Capabilities/Characteristics
    585
  - Transfer Overlay
    586
  - Endpoint Transfer Descriptor (Dtd)
    587
  - Device Operational Model
    589
  - Port State and Control
    590
  - Bus Reset
    592
  - Suspend/Resume
    593
  - Managing Endpoints
    594
  - Stalling
    595
  - Data Toggle Inhibit
    596
  - Priming Receive Endpoints
    597
  - Interrupt/Bulk Endpoint Bus Response Matrix
    598
  - Control Endpoint Operation Model
    599
  - Status Phase
    600
  - Isochronous Endpoint Operational Model
    601
  - Isochronous Pipe Synchronization
    602
  - Managing Queue Heads
    603
  - Queue Head Initialization
    604
  - Operational Model for Setup Transfers
    605
  - Building a Transfer Descriptor
    606
  - Transfer Completion
    607
  - Flushing/De-Priming an Endpoint
    608
  - Servicing Interrupts
    609
  - Deviations from the EHCI Specifications
    610
  - Discovery
    611
  - Operational Model
    612
  - Asynchronous Transaction Scheduling and Buffer Management
    613
  - Multiple Transaction Translators
    614
  - Embedded Design
    615
  - Port Speed Detection
    616
  - Features
    617
  - Overview
    618
  - The CAN System
    619
  - Module Disabled Mode
    620
  - Listen-Only Mode
    621
  - Flexcan Configuration Register (Canmcrn)
    622
  - Flexcan Control Register (Canctrln)
    624
  - Flexcan Free Running Timer Register (Timern)
    627
  - Flexcan Error Counter Register (Errcntn)
    629
  - Flexcan Error and Status Register (Errstatn)
    630
  - Interrupt Mask Register (Imaskn)
    632
  - Message Buffer Structure
    633
  - Functional Overview
    637
  - Arbitration Process
    638
  - Self-Received Frames
    639
  - Matching Process
    640
  - Locking and Releasing Message Buffers
    641
  - CAN Protocol Related Frames
    642
  - Time Stamp
    643
  - Flexcan Initialization Sequence
    645
  - Interrupts
    646
  - Block Diagram
    647

NXP Semiconductors MCF5253 Quick Start Manual (10 pages)

Brand: NXP Semiconductors | Category: Motherboard | Size: 1 MB

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Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors MCF5253 Manuals

NXP Semiconductors MCF5253 Reference Manual (648 pages)

Table of Contents

Chapter 1 MCF5253 Introduction

Chapter 2 Contents

Signal Description

Chapter 3 Coldfire Core

Chapter 4 Phase-Locked Loop and Clock Dividers

Chapter 5 Instruction Cache

Chapter 6 Static RAM (SRAM)

Chapter 7 Synchronous DRAM Controller Module

Chapter 8 Bus Operation

Chapter 9 System Integration Module (SIM)

Chapter 10 Chip Select Module

Chapter 11 General Purpose Timer Modules

Chapter 12 Analog to Digital Converter (ADC)

Chapter 13 IDE and Flash Media Interface

Chapter 14 DMA Controller

Chapter 15 UART Modules

Chapter 16 Queued Serial Peripheral Interface (QSPI) Module

Chapter 17 Audio Interface Module (AIM)

Chapter 18 I 2 C Modules

Chapter 19 Boot ROM

Chapter 20 Background Debug Mode (BDM) Interface

Chapter 21 IEEE 1149.1 Test Access Port (JTAG)

Chapter 22 USB, ATA DMA, and Clock Integration Module

Chapter 23 Advanced Technology Attachment Controller (ATA)

NXP Semiconductors MCF5253 Quick Start Manual (10 pages)

Table of Contents

1 Overview

2 Preparing the EVB for Operation

3 Running the USB Demonstration

4 The CF Flasher Tool

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