Resets; Identification Registers - NXP Semiconductors QorIQ LS1028A Reference Manual

4.1.1 Reserved Bits
Register
DUTCFG Read as 1. Write ones to unused bits.
others Read as 0. Write zeroes to unused bits.
Future definitions of reserved bits will maintain backward compatibility with the above
rules.

4.2 Resets

The reset values for registers are defined as follows:
4.2.1 Reset Actions
Term
NONE Register cannot be reset. Applies to read-only registers.
ARST Auxiliary Reset: registers are reset when the system powers up with standby power, and is never altered
by hardware again. Software writes are preserved.
CRST Control Reset: registers are not reset except under exceptional situations, such as power cycles or
watchdog timeout.
RRST Reconfig Reset: configuration registers are reset as with CRST unless a reconfiguration reset has been
requested.
GRST General Reset: always reset, for any reason.
Generally, a register is wholly affected by only one reset source, however there are
exceptions and these are shown with separate reset lines for each reset source.

4.3 Identification Registers

The ID block of registers contain values which identify the board, including major
revisions to the board and/or system controller FPGA or CPLD.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
Recommended Actions
Reset Action
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Chapter 4 Qixis Programming Model
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