Ethernet Controller Interface - NXP Semiconductors QorIQ LS1028A Reference Manual

Ethernet controller interface

2.8 Ethernet controller interface
The LS1028A processor supports one Ethernet controller (ENETC), which connects to an
onboard 1588 access header and an SGMII port (over LYNX36 SerDes Lane A). The
controller also supports QSGMII connectivity through the TSN switch and it is available
over LYNX36 SerDes interface (Lane B).
The EMI1 MDIO/MDC signals control the SGMII and QSGMII PHY transceivers. EMI1
operates at OVDD (1.8 V) levels. The signals are bi-directionally shifted to 2.5 V for
compatibility with both AR8033 (one-port SGMII) and F104S8A PHY (Four-port
QSGMII).
2.8.1 SGMII Ethernet
The onboard Ethernet PHY, Qualcomm AR8033 PHY (U23) connects to the ENETC of
the LS1028A processor using SGMII protocol over LYNX36 SerDes lane A.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
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