Board Configuration 2 (Brdcfg2) - NXP Semiconductors QorIQ LS1028A Reference Manual

Board Configuration 2 (BRDCFG2)

4.42.2 Function
The BRDCFG1 register shows/controls SYSCLK and DDRCLK speeds.
4.42.3 Diagram
Bits 7
R
W
RRST 00
4.42.4 Fields
Field
7-6 Reserved.
-
5-4 Reserved.
-
3-0 SYSCLK Frequency Selection:
SYSCLK 0010= 100.00 MHz (fixed)
All other values are reserved.
4.43 Board Configuration 2 (BRDCFG2)
4.43.1 Address
Register
BRDCFG2 052h
4.43.2 Function
The BRDCFG2 register reporst SerDes clock speeds for SerDes blocks 1 and 2.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
100
6 5 4
00
Confidential Proprietary
3 2
SYSCLK
Function
Offset
1 0
0010
NXP Semiconductors