Displayport; Serdes Interface - NXP Semiconductors QorIQ LS1028A Reference Manual

DisplayPort

USB controller. For USB2 port, the USB switch drives USB2 VBUS (USB2_VBUS)
when USB2_DRVVBUS=1, USB1_ID = 0, and USB2_CON_DET=1, this logic is
controlled by CPLD. For USB1 port, the USB switch drives USB1 VBUS
(USB1_VBUS) when USB1_DRVVBUS=1.
The maximum allowed current consumption of a USB connected device is 900 mA per
channel.
Both, USB1 and USB2 connectors have an LED nearby, USB1_5V and USB2_5V,
respectively, which are active when the +5 V USB power supply is enabled to the
connectors.
2.6 DisplayPort
The LS1028A processor supports and embedded DisplayPort (eDP) TX controller that
connects to the DisplayPort connector on the board for digital display.
The controller supports the following:
• Supports DisplayPort 1.3 and eDP 1.4
• Supports link transfer rates of up to HBR2 (5.4 Gbit/s) and display resolution up to
4Kp60
The CONFIG1 and CONFIG2 pins of the DisplayPort are pulled down with 1 MΩ
resistors to avoid any power driven on the DP_PWR pin from a downstream device.
The DP_PWR pin can provide 3.3 V up to 3 A inrush current through a power switch
NX5P3090UK (controlled through the CPLD register).

2.7 SerDes interface

The LS1028A processor supports one SerDes LYNX36 module with four high-speed
serial communication lanes to support various protocols, such as SGMII, QSGMII, PCIe,
and SATA.
The figure below shows the LS1028ARDB SerDes architecture.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
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