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NXP Semiconductors QorIQ LS1028A Reference Manual

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QorIQ LS1028A Reference Design
Board Reference Manual
Document Number: LS1028ARDBRM
Rev. A, 02/2018

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Summary of Contents for NXP Semiconductors QorIQ LS1028A

  • Page 1 QorIQ LS1028A Reference Design Board Reference Manual Document Number: LS1028ARDBRM Rev. A, 02/2018...
  • Page 2 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 3: Table Of Contents

    2.13 XSPI interface.................................39 2.14 JTAG port..................................41 2.15 eSDHC interface................................41 2.16 Mikro-click modules...............................43 2.17 GPIOs....................................45 2.18 Interrupt handling................................46 2.19 Temperature measurement..............................46 2.20 System controller ................................47 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 4 4.18 Reconfiguration Registers...............................77 4.19 Reconfiguration Control (RCFG)........................... 77 4.20 USB Control (USB_STAT)............................79 4.21 USB Control (USB_CTL).............................. 79 4.22 Watchdog (WATCH)..............................80 4.23 Power Control/Status Registers............................82 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 5 4.48 DUT Configuration Registers............................106 4.49 DUT Configuration 0 (DUTCFG0)..........................106 4.50 DUT Configuration 1 (DUTCFG1)..........................107 4.51 DUT Configuration 2 (DUTCFG2)..........................108 4.52 DUT Configuration 11 (DUTCFG11)..........................109 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 6 Section number Title Page 4.53 Core Management Space Registers..........................110 4.54 Core Management Address (CMSA)..........................111 4.55 Core Management Data (CMSD)........................... 112 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 7: Ls1028Ardb Overview

    Chapter 1 LS1028ARDB Overview ® The QorIQ LS1028A reference design board (LS1028ARDB) is a computing, evaluation, development, and test platform supporting the QorIQ LS1028A processor, ® ® which is a dual-core Arm Cortex -v8 A72 processor with frequency up to 1.3 GHz. The LS1028ARDB is optimized to support SGMII (1 Gbit/s), QSGMII (5 Gbit/s), PCIe x1 (8 Gbit/s), and SATA (6 Gbit/s) over high-speed SerDes ports, USB 3.0, DisplayPort, and...

  • Page 8: Acronyms And Abbreviations

    Offline configuration manager On-The-Go Pre-boot loader Phase-locked loop PMIC Power management multi-channel IC Power-on reset Power supply unit Precision time protocol Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 9: Related Documentation

    Provides a detailed description about the LS1028A QorIQ multicore processor and its Manual features, such as memory map, serial interfaces, power supply, chip features, and clock information Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 10: Block Diagrams

    Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect and Debug Networking Elements Figure 1-1. LS1028A block diagram The figure below shows the LS1028ARDB block diagram. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 11: Board Features

    POWER SUPPLIES (VDD, GVDD, etc.) ENETC (1588) IEEE1588 FANS Connector Figure 1-2. LS1028ARDB block diagram 1.4 Board features The table below lists the features of the LS1028ARDB. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 12 • Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 data cache • Arranged as a single cluster of two cores sharing a single 1 MB L2 cache NOTE: For more details on the LS1028A processor, see QorIQ LS1028A Family Reference Manual. DDR memory DDR4 •...
  • Page 13 • Package type is Flip Chip, Plastic-ball, Grid Array (FC-PBGA), 17 mm x 17 mm • Socket and heat sink are included System logic CPLD • Manages the following: QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 14 Specification Description • System reset sequencing • SoC POR configuration at reset • Implements registers for system control and monitoring • General fault monitoring and logging QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 15: Ls1028Ardb Functional Description

    System controller 2.1 Processor The LS1028ARDB board is based on the QorIQ LS1028A processor having two Arm® Cortex®- A72 processor cores. The LS1028ARDB board supports as many features of the LS1028A as possible. In addition, the LS1028ARDB board supports an LS1043A interposer that allows early evaluation of the board with limited features and restrictions.

  • Page 16: Power Supplies

    CAN TRANSCEIVERS MIKROBUS CONNECTORS LEDs MISC PARTS (BUFFERS & TRANSLATORS USB_HVDD LS1028 USB_HVDD LPF x2 3.3V @ .45 A Figure 2-1. Power supplies - Part 1 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 17 The figure below shows the filters used. 5.1OHm 0.33OHm 2.2uF 2.2uF 10uF 47uF 4.7uF 0.22uF 2.2uF=NFM18P C225B1A3 2.2uF=G RM155R 60J225K E95 Figure 2-3. Passive low pass filters QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 18 0.6 V at 3 A Address and control bus termination supply MVREF 0.6 V at 3 A Reference voltage for DDR4 DRAM memories Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 19 0.9 V / 1.0 V at 0.15 Power supply for TA_BB_VDD. Integrated 1. VDD is 1.0 V or 0.9 V depending upon the state of GPIO1_DAT24 GPIO pin of LS1028A. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 20 On the availability of 12 V supply to the power regulators, the orderly enable of all power supplies are sequenced using powergood of the regulators, as shown in the following figure. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 21 LDO4 (PS_DDR_EN) DDR4 (1.2V, VTT, VREF) MC34716 Internal delay from last SEQ EVENT RST_OUT (to CPLD) VR500 RST_OUT Figure 2-4. Power up voltage sequence QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 22: Clocks

    2.3 Clocks The LS1028ARDB provides all the clocks required for the processor and peripheral interfaces. The figure below shows the LS1028ARDB clock architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 23 • Frequency: 25 MHz CPLD • Output type: LVCMOS • Operating voltage: 3.3 V OUT3,5: • Frequency: 100 SerDes1 controller SD1_REF_CLK1_[P, N] SD1_REF_CLK2_[P,N] Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 24: Ddr Interface

    The LS1028ARDB board connects four 1G x8 DDR4 SDRAM memory chips supporting data transfer rates of up to 1.6 GT/s and one 1G x8 DDR4 SDRAM memory chip supporting ECC. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 25 VTT (0.6 V) and VREFCA (0.6 V). The memory interface including all the necessary termination and I/O power are routed, as shown in the following figure. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 26: Usb Interface

    (DFP) or upstream facing port (UFP). Based on the configuration detected on the Type C port, the USB2 PHY can operate either in host or device mode. The following figure shows the architecture of the USB 3.0 interface. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 27 The USB switch is powered from +5 V USB power supply. To indicate power fault conditions, the USB switch sends PWRFAULT signals to the QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 28: Displayport

    The LS1028A processor supports one SerDes LYNX36 module with four high-speed serial communication lanes to support various protocols, such as SGMII, QSGMII, PCIe, and SATA. The figure below shows the LS1028ARDB SerDes architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 29 3 / D PCIe Gen 3 (8 Gbit/s) M.2 Key E slot for Wi-Fi cards SATA 3.0 (6 Gbit/s) M.2 Key B slot for SATA based SSD cards QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 30: Ethernet Controller Interface

    2.8.1 SGMII Ethernet The onboard Ethernet PHY, Qualcomm AR8033 PHY (U23) connects to the ENETC of the LS1028A processor using SGMII protocol over LYNX36 SerDes lane A. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 31 R413, R414, R415 & R416 : MO DE 0001 Figure 2-9. SGMII and IEEE 1588 Table 2-5. Hardware bootstrap settings for SGMII PHY Setting Description PHY_AD[2:0] PHY address = 0b00010 MODE[3:0]=0001 SGMII<=>UTP QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 32 10K DNP Figure 2-10. QSGMII port Table 2-6. Hardware bootstrap settings for QSGMII PHY Setting Description PHY_AD[4:2] PHY address = 0b100 Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 33: Connectors

    Table 2-8 to support solid state storage devices (SSD) ( SATA 3.0). The M.2 Key B connector supports 2230 and 2242 module card types. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 34: Duart Interface

    It is recommended to use UART1 as a debug port. The LTC2804-1 transceiver can support 1 Mbit/s data rate on each of the serial ports. The figure below shows the LS1028ARDB DUART connections. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 35: Can Interface

    CAN signals to and from the processor. The TJA1052T/3 transceivers can support data rate of up to 5 Mbit/s in CAN with Flexible Data-Rate (CAN FD) phase. The figure below shows the CAN architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 36: I2C Interface

    (1.8 V to 3.3 V and 3.3 V to 1.8 V) for CPLD and external I2C devices. The figure below shows the I2C bus architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 37 All channels on I2C1 are translated to 3V3 except channel 1, which operates at 1V8 (OVDD) power supply. The I2C devices available on the I2C1 bus are shown in the figure below. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 38 Write protectable. 0x57 Atmel AT24C02C-XHM-B: System ID Stores board-specific 256-byte EEPROM data, such as MAC addresses and serial number/errata. Write protectable. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 39: Xspi Interface

    QSPI emulation. The XSPI chip-select signals from the processor are driven to the XSPI memories or to the QSPI emulator through two high-speed multiplexers. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 40 QSPI flash emulator (DediProg EM100Pro) through an ISP-ADP-intel-B cable adapter. The EM100Pro emulator uses 1.8 V as the input/output voltage. The table below describes the XSPI routing configuration. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 41: Jtag Port

    JTAG connector for debugging purposes. The following figure shows the LS1028ARDB JTAG architecture. LS1028 (4x) 100 W 1/4W DUT_TMS DUT_TCK JTAG OVDD DUT_TDO (1.8V) DUT_TDI Header PIN-M-180-1.27mm TBSCAN_EN_B JTAG_RST_B to CPLD 1.8V Figure 2-15. JTAG architecture QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 42: Esdhc Interface

    SDHC_VSEL value. Table 2-13. EVDD switch output voltage SD card speed SDHC_VSEL EVDD switch voltage Default or high speed 3.3 V Ultra-high speed (UHS) 1.8 V QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 43: Mikro-Click Modules

    I2C on both the modules can be accessed instantaneously from the I2C mux. For more information on I2C mux selection, refer interface. The following figure shows the mikroBUS architecture. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 44 However, only one mikroBUS connector can be used at a time as SPI3 supports only one chip select. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 45: Gpios

    GPIO1_DAT24 controls the VDD regulator and is used to change the VDD value from 1.0 V to 0.9 V as described in the following table. Table 2-16. GPIO1_24 setting GPIO Setting GPIO1_24 High (default) 1.0 V GPIO1_24 0.9 V QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 46: Interrupt Handling

    I2C write Description 0x77 0x0B 0x0B Program primary I2C bus multiplexer (PCA9848PWJ) to get access to I2C1_CH3 (I2C sub-channel for SA56004ED) Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 47: System Controller

    • System alert monitoring and status display • Remapping of system boot devices • Handling of board control and status registers The following figures show the system controller architectural details. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 48 BOM rev PCB_REV[2:0] 000 = “Rev A” 001 = “Rev B” Selectively DNP resistors to encode PCB rev Figure 2-18. System controller architecture QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 49 The system controller is powered using the 3.3 V and 1.8 V regulators. The CPLD controls the reset of the board peripherals including the LS10128A processor. However, the CPLD does not control power sequencing. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 50 Specifies RCW fetch location CFG_RCW_SRC1 UART1_SOUT CFG_RCW_SRC2 ASLEEP CFG_RCW_SRC3 CLK_OUT TEST_SEL_B TEST_SEL SW3[1] DUTCFG2[0] Silicon variations CFG_SVR[0:1] XSPI_CS0_B DUTCFG2[2:1] XSPI0_CS1_B CFG_ENG_USE0 XSPI_SCK DUTCFG11[7] Configures processor to use differential SYSCLK. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 51 Device resets are asserted: • RST_QSGMII_B • RST_1GETH_B • PEXM2_1_PERST0_B • PEXM2_2_PERST0_B • SATAM2_3_PERST0_B • RST_IEEE1588_B • RST_I2C_B • RST_MEM1_3V3_B Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 52 If RCW data is correct, then the system starts running the code. If there is an error, then RESET_REQ_B is asserted and the system halts. Reset sequence complete. The CPLD has finished reset management. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 53 Table 2-21. Reset sequence Controller Step Action Description The reset sequencer watches for reset switch events and will restart at reset sequencer step 1 if any are detected. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 54 System controller QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 55: Board Configuration And Debug Support

    LS1043A processor is installed. SW1[5] Reset mode SW_RST_MODE RESET_REQ_B • 0: Ignore RESET_REQ_B • 1: Trigger system reset on RESET_REQ_B (default value) Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 56 • 1: Write-protect SYSID and UEFI flash (default value) SW3[5] Boot Box mode SW_BOOTBOX_B • 0: Enable boot-box mode • 1: Normal operating mode (default mode) Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 57: Leds

    5 V power is supplied to the USB 1 connector for external devices Yellow ASLEEP The processor has not exited Sleep mode, which generally indicates: • Improper RCW source selection Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 58 Green TA_BB_VDD Low power security monitor supply is operating correctly Green SocInSocket Indicates that the LS1028A processor is in socket Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 59 1011 = 0xB Start reset due to (cause): Watchdog timeout RST_BY_REG 1100 = 0xC Start reset due to (cause): Register bit set Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 60 Start reset due to (cause): Pushbutton switch RECONFIG 1110 = 0xE Start reset due to (cause): Reconfig request POST_RST 1111 = 0xF Recover from requester reset QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 61 Watchdog (WATCH) xxxxxxxb 021h Power Control 2 (PWR_CTL2) 00000000b 024h Power Status 0 (PWR_MSTAT) 110010xxb 025h Power Status 1 (PWR_STAT1) 1xxx1111b Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 62: Register Conventions

    If you attempt to read such addresses, undefined data is returned. Undefined register addresses may be defined in the future. For registers which do not define all bits, reserved bits behave as follows: QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 63: Resets

    4.3 Identification Registers The ID block of registers contain values which identify the board, including major revisions to the board and/or system controller FPGA or CPLD. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 64: Identification (Id)

    The ID number remains same for all board revisions. 4.4.3 Diagram Bits NONE 4.4.4 Fields Field Function The board-specific identifier for the system. 47h= LS1028ARDB 4.5 Board Version (VER) QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 65 The BRD field lets end users determine the version of the board. Software can use this field to print board version identification. For example: printf("Board Version: %c", (get_pixis( VER ) & 0Fh) + 'A' - 1 ); QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 66: Qixis Version (Qver)

    4.6.3 Diagram Bits QVER NONE 00000001 4.6.4 Fields Field Function Qixis version as a decimal value: QVER 1= Version 1 2= Version 2 4.7 Programming Model (MODEL) QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 67 0010= Revision 2 : PCB version is 'A2', 'B2', etc. and so forth. Note that this field should be appended to the VER.PCB information only if non-zero. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 68: Minor Revision (Minor)

    4.8.3 Diagram Bits INFO NONE 4.8.4 Fields Field Function 0h= The minor revision number, increases on each distribution. INFO 8h= Bits 31-24 of the 32bit build date. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 69: Control And Status Registers

    4.10.1 Address Register Offset 005h 4.10.2 Function The CTL register is used to control various aspects of the target system. 4.10.3 Diagram Bits XTEST CFGWP FAIL CRST QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 70: Auxiliary (Aux)

    The AUX register may be used by software to store information. The AUX register is initialized to zero when the system is powered-up, and never altered by hardware again. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors...

  • Page 71: System Status (Stat_Sys)

    4.12 System Status (STAT_SYS) 4.12.1 Address Register Offset STAT_SYS 009h 4.12.2 Function The STAT_SYS register reports general system status. 4.12.3 Diagram Bits ALTERED ASLEEP NONE 00000 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 72: Alarm (Alarm)

    Write 1 to an ALARM register bit to prevent Qixis from recognizing that alarm condition. By default, all alarms are handled. 4.13.3 Diagram Bits TWARN TALERT ARST 0000 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 73: Presence Detect 1 (Stat_Pres1)

    4.14 Presence Detect 1 (STAT_PRES1) 4.14.1 Address Register Offset STAT_PRES1 00Bh 4.14.2 Function The STAT_PRES1 register detects the presence and type of processor installed. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 74: Presence Detect 2 (Stat_Pres2)

    0= Processor type (CPUID) is based on device. 1= Processor type (CPUID) was overridden using SW_CPU_FORCE. Reserved. 4.15 Presence Detect 2 (STAT_PRES2) 4.15.1 Address Register Offset STAT_PRES2 00Ch QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 75: Misc Status (Stat_Misc)

    0= a module is detected in M.2 connector #1 (PEX). M2_1 1= no module is detected. 4.16 Misc Status (STAT_MISC) 4.16.1 Address Register Offset STAT_MISC 00Dh QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 76: Led Control (Led)

    Field Function DP Power Fault: DPFLT 0= DP_PWR is reporting fault (overcurrent). 1= DP_PWR operating normally. Reserved. 4.17 LED Control (LED) 4.17.1 Address Register Offset 00Eh QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 77: Reconfiguration Registers

    SYSCLK frequencies, boot device selections, or any other configuration controlled by a BRDCFG or DUTCFG register. 4.19 Reconfiguration Control (RCFG) QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 78 NOTE: This is not a highly-secure watchdog; software can reset this bit at any time and disable the watchdog. Reserved. Reconfiguration Start: 0= Reconfiguration sequencer is idle. 1= On the 0-to-1 transition, the reconfiguration process begins. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 79: Usb Control (Usb_Stat)

    U2CON 0= No connection detected. 1= Connection detected. USB2 ID Status: U2ID 0= USB2 ID is low (DFP mode). 1= USB2 ID is high (UFP mode). QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 80: Watchdog (Watch)

    10= Force USB1_PWRFAULT low (mask power-faults). 11= Force USB1_PWRFAULT high (trigger a power-fault condition). USB2 Fault Control: UFC2 10= Normal operation. 11= Force signal USB2_PWRFAULT high (trigger a power-fault condition). Reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 81 Watchdog timer value, as determined by the formula: WATCH time-out = [ WATCH * (2.0sec) ] + 2.0sec Examples: 11111111= 8 min 00111111= 2 min 00001111= 32 sec QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 82: Power Control/Status Registers

    4.24 Power Control 2 (PWR_CTL2) 4.24.1 Address Register Offset PWR_CTL2 021h 4.24.2 Function The PWR_CTL2 register is used to control system power-on/power-off events. 4.24.3 Diagram Bits CRST 0000000 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 83: Power Status 0 (Pwr_Mstat)

    The PWR_MSTAT register monitors the overall power status of the board, including that of the main (ATX or other) power supply used to power all other rails. 4.25.3 Diagram Bits ATXON ATXGD FAULT PWROK SSTATE NONE QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 84: Power Status 1 (Pwr_Stat1)

    The PWR_STAT1 registers is used to monitor the status of individual power supplies. If a bit is set to '1', the respective power supply is operating correctly. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 85: Clock Control Registers

    1= Power supply is operating. 4.27 Clock Control Registers The clock control registers control programmable clock synthesizers used to supply clocks to the processor and associated peripherals. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 86: Clock Speed 1 (Clk_Spd1)

    UART baud rates, I2C clock rates, and DDR memory timing. 4.28.3 Diagram Bits SYSCLK NONE 0000 0010 4.28.4 Fields Field Function Reserved. SYSCLK Rate Selection: SYSCLK 0010= 100.00 MHz (fixed) Other values are Reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 87: Clock Id/Status (Clk_Id)

    Bits NONE 0000 0000 4.29.4 Fields Field Function Reserved. System Clock ID = 0000 (NONE) CLK0= SYSCLK is fixed on this system. 4.30 Reset Control Registers QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 88: Reset Control (Rst_Ctl)

    11= Normal - assert PORESET_B to DUT to begin normal reset sequence. DDR Reset Lock: DDRLK 0= Reset is asserted to the DDR DIMMs/devices normally. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 89: Reset Status (Rst_Stat)

    The RST_STAT register reports the current status of various reset-related signals. 4.32.3 Diagram Bits WAIT SYSRST HRST PORST RREQ NONE 4.32.4 Fields Field Function Reset Waiting: Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 90: Reset Event Trace (Rst_Reason)

    4.33 Reset Event Trace (RST_REASON) 4.33.1 Address Register Offset RST_REASON 042h 4.33.2 Function The RST_REASON register is used to report the cause of the most-recent reset cycle. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 91: Reset Force 1 (Rst_Force1)

    0101= RCFG[GO] (that is, reconfiguration reset) was asserted. 0110= RESET_REQ_B assertion (from processor) was asserted. 1111= No event recorded yet. 4.34 Reset Force 1 (RST_FORCE1) 4.34.1 Address Register Offset RST_FORCE1 043h QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 92: Reset Force 2 (Rst_Force2)

    Function 1= Assert RST_XSPI_B. XSPI Reserved. 1= Assert RST_I2CMUX_B. I2CMUX 1= Assert RST_EMMC _B EMMC Reserved. Reset DDR. 1= Assert RST_MEM_B 4.35 Reset Force 2 (RST_FORCE2) QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 93 1= Assert DUT_PORESET_B. PORST NOTE: This bit only asserts the signal to the DUT; it is not intended to be used as a general system reset. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 94: Reset Force 3 (Rst_Force3)

    M2_2 M2_3 IEEE GRST 0000 4.36.4 Fields Field Function 1= Assert RST_PEXM2_1_B. M2_1 1= Assert RST_PEXM2_2_B. M2_2 1= Assert RST_SATAM2_3_B. M2_3 Reserved. 1= Force RST_IEEE1588_B. IEEE QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 95 4.37.3 Diagram Bits XSPI I2CMUX EMMC ARST 4.37.4 Fields Field Function 1= Mask RST_XSPI_B. XSPI Reserved. 1= Mask RST_I2CMUX_B. I2CMUX Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 96: Reset Mask 2 (Rst_Mask2)

    Mask selected reset sources. See RST_FORCE1 for details. 4.38.3 Diagram Bits QSGMII TRST HRST PORST ARST 4.38.4 Fields Field Function 1= Mask RST_QSGMII_B. QSGMII Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 97: Reset Mask 2 (Rst_Mask3)

    4.39 Reset Mask 2 (RST_MASK3) 4.39.1 Address Register Offset RST_MASK3 04Dh 4.39.2 Function Mask selected reset sources. See RST_FORCE1 for details. 4.39.3 Diagram Bits M2_1 M2_2 M2_3 IEEE ARST 0000 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 98: Board Configuration Registers

    4.41 Board Configuration 0 (BRDCFG0) 4.41.1 Address Register Offset BRDCFG0 050h 4.41.2 Function The BRDCFG0 register is used to select between the XSPI NOR, the XSPI NAND, or an XSPI QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 99: Board Configuration 1 (Brdcfg1)

    1= Serial NAND device (MT29F4G01ABBFD12 or equivalent). The default is 0, unless booting from an XSPI NAND is selected. 4.42 Board Configuration 1 (BRDCFG1) 4.42.1 Address Register Offset BRDCFG1 051h QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 100: Board Configuration 2 (Brdcfg2)

    4.43 Board Configuration 2 (BRDCFG2) 4.43.1 Address Register Offset BRDCFG2 052h 4.43.2 Function The BRDCFG2 register reporst SerDes clock speeds for SerDes blocks 1 and 2. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 101: Board Configuration 3 (Brdcfg3)

    SerDes1 Clock #2 Rate: SD1CK2 00= 100.000 MHz (fixed) Reserved. 4.44 Board Configuration 3 (BRDCFG3) 4.44.1 Address Register Offset BRDCFG3 053h 4.44.2 Function The BRDCFG3 register controls board routing. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 102: Board Configuration 4 (Brdcfg4)

    00= Routed to RS232 transceiver and DB9 connector P1A (default). 01= reserved. 10= Routed to uBUS1 module. 11= Routed to uBUS2 module. Reserved. 4.45 Board Configuration 4 (BRDCFG4) 4.45.1 Address Register Offset BRDCFG4 054h QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 103: Board Configuration 5 (Brdcfg5)

    0= Clock is enabled (default). 1= Clock is disabled. DisplayPort Power Enable (net DP_PWR_EN): DPPWR 0= DP_PWR is disabled. 1= DP_PWR is enabled (default). Reserved. 4.46 Board Configuration 5 (BRDCFG5) QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 104 10= IRQ pin treated as output, asserted low. 11= IRQ pin treated as output, asserted high. Manages the uBUS1 RST output pin: U1RST 00= RST pin tri-stated. 01= reserved. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 105: Board Configuration 6 (Brdcfg6)

    U2I reports the current 3.3V LVTTL level on the IRQ interrupt pin. U2R reports the current 3.3V LVTTL level on the RST pin. Reserved. Table continues on the next page... QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 106: Dut Configuration Registers

    4.49 DUT Configuration 0 (DUTCFG0) 4.49.1 Address Register Offset DUTCFG0 060h 4.49.2 Function The DUTCFG0 register is used to the RCW location setting (cfg_rcw_src). QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 107: Dut Configuration 1 (Dutcfg1)

    Note that the RCW_SRC settings are mapped to equivalent 9-bit values when an LS1043A interposer is connected. 4.50 DUT Configuration 1 (DUTCFG1) 4.50.1 Address Register Offset DUTCFG1 061h QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 108: Dut Configuration 2 (Dutcfg2)

    Reserved. 4.51 DUT Configuration 2 (DUTCFG2) 4.51.1 Address Register Offset DUTCFG2 062h 4.51.2 Function The DUTCFG2 register manages device selection (SVR) and internal-only device test features. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 109: Dut Configuration 11 (Dutcfg11)

    06Bh 4.52.2 Function The DUTCFG11 register is used to control the CFG_ENG_USE[7:0] signals. The function of these bits are defined by silicon engineers for special use. QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...

  • Page 110: Qoriq Ls1028A Reference Design Board Reference Manual, Rev. A, 02/2018

    Image of configuration switch #n. Ranges not listed are reserved. A standard use of the CMSA/CMSD port is to read the state of configuration switches, for example: QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 111 CMSD register. 4.54.3 Diagram Bits ADDR ARST 00000000 4.54.4 Fields Field Function Select internal CMS register for read/write via CMSD. ADDR QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 112 CMSD contains the value of a CMS register selected by CMSA. See CMSA for details. 4.55.3 Diagram Bits DATA ARST 00000000 4.55.4 Fields Field Function Read/write internal CMS registers selected with CMSA. DATA QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 113 Revision History The table below summarizes the revisions to this document. Table A-1. Revision history Revision Date Topic cross-reference Change description Rev. A 02/2018 Initial NDA revision QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 114 QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018 NXP Semiconductors Confidential Proprietary...
  • Page 115 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based nxp.com on the information in this document.

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