NXP Semiconductors QorIQ LS1028A Reference Manual page 32

Ethernet controller interface
2.8.2 QSGMII Ethernet
The onboard Ethernet PHY, NXP F104S8A PHY (U24), connects to the TSN switch of
the LS1028 processor using QSGMII protocol over SerDes lane B.
The following figure shows the QSGMII interface.
LS1028
SERDES RX
(LANE-B)
TX
EMI1_MDC
EMI1_MDIO
GPIO1_25
IDT
CLKGEN
OUT1 (LVDS)
5P49V5907B520NDGI
Table 2-6. Hardware bootstrap settings for QSGMII PHY
Setting
PHY_AD[4:2]
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
32
2V5 2V5
1.5K 1.5K
TRANSLATOR
MAX14591
1.8V  2.5V
3V3
4.7K
SYSTEM
RST_QSGMII
CPLD
3V3
4.7K
100MHz
PHY #2
R178 : P HY ADDRES S[4:2] = 'b 100
Figure 2-10. QSGMII port
PHY address = 0b100
Table continues on the next page...
Confidential Proprietary
NXP F104S8A
138-PIN QFN
PHY #2
P0_D0P/N
RDP/N_0
P0_D1P/N
P0_D2P/N
Transformer
P0_D3P/N
TDP/N_0
P1_D0P/N
P1_D1P/N
P1_D2P/N
Transformer
MDC P1_D3P/N
MDIO
P2_D0P/N
P2_D1P/N
NRESET
P2_D2P/N
P2_D3P/N
P3_D0P/N
P3_D1P/N
MDINT
P3_D2P/N
P3_D3P/N
VDD25
VDDA25
REFCLK_P/N
VDD
VDDA
10K DNP PHYADDR2 R179 10K DNP
R185
PHYADDR3
R180
10K DNP
R177 10K DNP
PHYADDR4
R178 R182
10K 10K DNP
Description
NXP Semiconductors
1GB
#1
RJ-45 with
ACT
1GB
#2
RJ-45 with
ACT
1GB
#3
RJ-45 with
Transformer
ACT
1GB
#4
RJ-45 with
Transformer
ACT
2V5
1V0
2V5