NXP Semiconductors QorIQ LS1028A Reference Manual page 13

LS1028ARDB feature
CAN Two CAN ports (CAN1
and CAN2)
Ethernet SGMII (1 GB Ethernet
port)
QSGMII (four 1 GB
Ethernet ports)
IEEE 1588
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
Display DisplayPort (not
supported by the
LS1043A processor)
Clocks Differential system
clock (DIFF_SYSCLK)
SerDes clocks
Ethernet clocks
Display Port clock
(DP_REFCLK)
FPGA CLK
Power supplies
Debug interface
Package
System logic CPLD
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
Table 1-3. LS1028ARDB features (continued)
Specification
The two CAN DB9 ports can support CAN FD fast phase at data rates of
up to 5 Mbit/s.
• Five 1G/100M/10BaseT Ethernet ports supported. One port is
supported on SGMII ENET MAC and the other four through the TSN
switch.
• Five RJ45 connectors with link and activity status are used with the
SGMII and QSGMII interfaces
™
• IEEE 1588 precision time protocol (PTP) is supported through an
onboard header (J11) and SMA connector (J12) on the
PULSE_OUT1 signal for 1PPS timing signal generation
• Supports super-speed (5 Gbit/s) operations
• USB 3.0 port 1 is configured as host with a Type A connector
• USB 3.0 port 2 is configured as downstream facing port (DFP) or
upstream facing port (UFP) with a Type C connector
• Supports display resolution of up to 4Kp60
• Supports link transfer rates of up to HBR2 (5.4 Gbit/s)
100 MHz
REF_CLK1 and REF_CLK2 of 100 MHz
125 MHz clock to Ethernet controller either from the IEEE 1588 port or an
onboard oscillator
27 MHz
25 MHz clock to CPLD
• 12 V input power from DC input adaptor
• 5.0 V for USB1, USB2, CAN1, CAN2, and mikro-click modules
• 1.0 V (VDD) for core and platforms
• Filtered 1.0 V / 0.9 V USB_SDVDD, USB_SVDD, DP_SVDD, SVDD
• 3.3 V for board components (SGMII PHY, M.2 connectors, SD card,
eMMC, CAN transceivers, mikroBUS connectors, LEDs, DP port,
CPLD IO and VDD, clockgen VDDO)
• Filtered 3.3 V for USB_HVDD
• 1.8 V for board components (UART transceivers, XSPI memories,
eMMC memory IO VDD, CPLD IO bank3)
• 1.8 V clockgen VDD and VDDA
• 1.8 V OVDD, TH_VDD
• Filtered 1.35 V X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2
• 2.5 V QSGMII PHY VDD25, VDD25A, and DDR4 memory VPP
• 1.0 V QSGMII PHY VDD, VDDA
• 1.2 V DRAM VDD
• 0.6 V DRAM VTT, VREF
• 3.3 V / 1.8 V EVDD for eSDHC
• 0.9 V / 1.0 V TA_BB_VDD
• Arm Cortex 10-pin JTAG connector
• CPLD programming header
• Package type is Flip Chip, Plastic-ball, Grid Array (FC-PBGA), 17
mm x 17 mm
• Socket and heat sink are included
• Manages the following:
Confidential Proprietary
Chapter 1 LS1028ARDB Overview
Description
13