Related Manuals for NXP Semiconductors QorIQ T2080
Summary of Contents for NXP Semiconductors QorIQ T2080
- Page 1 NXP Semiconductors Document identifier: T2080RDBPCUG User Guide Rev. 1, 08/2021 QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide...
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Page 2: Table Of Contents
3.1.8 Thermal control and status register (THMCSR)................35 3.1.9 Panel LED control and status register (LEDCSR)..............36 3.1.10 SFP+ control and status register (SFPCSR)................37 3.1.11 Miscellanies control and status register (MISCCSR).............. 38 QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 2 / 44... - Page 3 3.1.12 Boot configuration override register (BOOTOR)..............39 3.1.13 Boot configuration register 1 (BOOTCFG1)................39 3.1.14 Boot configuration register 2 (BOOTCFG2)................40 Appendix A Revision history................42 QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 3 / 44...
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Page 4: Chapter 1 Overview
Dual In-Line Package Direct Memory Access DPAA Data Path Acceleration Architecture DRAM Dynamic Random Access Memory Device Under Test Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 4 / 44... -
Page 5: T2080 Silicon Features
— Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling • One 32/64-bit DDR3 SDRAM memory controller: — DDR3 and DDR3L with ECC and interleaving support QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 5 / 44... -
Page 6: T2080Rdb-Pc Board Features
◦ SerDes-1 Lane E-H: to PCIe slot (PCIe4 x4, Gen3) ◦ SerDes-2 Lane A-D: to PCIe Goldfinger (PCIe1 x4, Gen2) ◦ SerDes-2 Lane E-F: to C293 secure coprocessor (PCIe2 x2) QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 6 / 44... - Page 7 — MicroSD port connects directly to MicroSD or TF • SPI — Onboard support of SPI flash • Other I/O — Two serial ports — Two I2C ports QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 7 / 44...
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Page 8: Block Diagram
2 x USB2.0 w/PHY 8 lanes up to 10 GHz SerDes 8 lanes up to 8 GHz SerDes Clocks/reset GPIO CCSR Figure 1. T2080 block diagram QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 8 / 44... - Page 9 Local Bus (8bit) MT29F8G08ABABAWP-12IT (1GB) TXD,RXD,RTS,CTS RJ45 MAX3232 SPI FLASH TXD,RXD,RTS,CTS SPI Bus RJ45 MAX3232 N25Q512A13GSF40F (64MB) SDHC Bus Micro SD card Figure 2. T2080RDB-PC architecture QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 9 / 44...
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Page 10: Chapter 2 Architecture
The power supplies provided are organized into general categories and are described in the individual sections. The diagram below shows the power supply architecture. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 10 / 44... -
Page 11: Reset
CPLD manages the reset signals to and from the T2080 processor and other devices on the T2080RDB-PC. The diagram below shows an overview of the reset architecture. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide... -
Page 12: Clocks
• DDRCLK (single-ended and differential) • SerDes clocks • Ethernet clocks • USB clock The architecture of the clock section is shown in the diagram below. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 12 / 44... -
Page 13: Ddr
I/O power and is routed to achieve maximum performance of the memory bus, as shown in the diagram below. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 13 / 44... -
Page 14: Serdes Port
• PCI Express (PEX) Gen 3 1X 8 Gbit/s • XFI 1X 10.3125 Gbit/s An overview of the SerDes protocols, which are supported on the T2080RDB, is shown in the table below. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 14 / 44... -
Page 15: Pci Express Support
The T2080 supports evaluation of the XFI protocol using Cortina CS4315 dual port 10G CDR. 10G data is carried over the XFI interface. The image below shows the connectivity of XFI interface. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide... -
Page 16: Xfi 10Gbase-T Port Support
T2080RDB-PC, the EC1 and EC2 ports only operate in RGMII mode. Both ports connect to Realtek RTL8211 PHYs. The image below shows the connectivity of EC1/EC2 interface. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide... -
Page 17: Ethernet Management Interface
EMI1_MDIO RTL8211E-VB PHY_ADDR=0x02 (RGMII PHY) T2080 EMI2_MDC PHY1_ADDR=0x0C CS4315 10G CDR EMI2_MDIO PHY2_ADDR=0x0D AQR113C PHY1_ADDR=0x00 10G-BASET AQR113C PHY2_ADDR=0x08 10G-BASET Figure 11. EMI hardware block QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 17 / 44... -
Page 18: I2C
Channel 1 I2C2_SFP2_SDA 0x50 I2C2_SCL I2C2 PCA9546 I2C2_SDA I2C2_CHAN2_SCL NOT USE Channel 2 I2C2_CHAN2_SDA I2C2_PEX4S_SCL PCle SLOT I2C2_PEX4S_SDA Channel 3 I2C_ADDR-0X77 Figure 12. I2C subsystem QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 18 / 44... -
Page 19: Spi Interface
Booting from eSDHC interface is supported using the on-chip ROM of the processor. On T2080RDB-PC, a single connector is used for MicroSD memory cards, as shown in the image below. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide... -
Page 20: Usb Interface
T2080 for individual port management. The image below shows how the USB connectivity is implemented on the T2080RDB-PC. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 20 / 44... -
Page 21: Rs-232
The serial connection is typically configured to run at 11.5 Kbit/s. Each UART supports: • Full-duplex operation • Software-programmable baud generators • Software-selectable serial interface data format, that includes: — Data length QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 21 / 44... -
Page 22: Jtag/Cop Port
Ethernet port, USB port, parallel port, or RS-232. A typical setup using a USB port emulator is shown in the image below. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide... - Page 23 VDD_SENSE Pulled to 3.3 V using a 10 Ohm resistor. Connected directly between the processor and JTAG/COP connector. Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 23 / 44...
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Page 24: Connectors, Headers, Jumper, Push Buttons, And Leds
10GBase-T J13, J15 Ethernet ports 10G optics Dual Type A USB J35 (2 ports) UART Battery holder SODIM Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 24 / 44... -
Page 25: Headers
Used for resetting the whole board. Power on/off Used for turning the power on or off. 2.16.5 LEDs Table 10 lists all the LEDs on the T2080RDB-PC front plate. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 25 / 44... -
Page 26: Temperature
The ADT7481 temperature warning and alarm signals are connected to the CPLD for monitoring. CPLD uses these signals to adjust CPU FAN speed and protect the CPU from over-temperature failure. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide... -
Page 27: Dip Switch Definition
In order to use the CPLD override option, software sets an override bit, that allows the CPLD to override the switch setting during power-on reset. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 27 / 44... - Page 28 1: DDR3L (1.35 V) SW2[8] cfg_rsp_dis IFC_AVD Reserved Reserved SW3[1] cfg_eng_use0 IFC_WE0 Sys_clock selection 1: Single sys_clk is selected Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 28 / 44...
- Page 29 (CS0 is connected to NOR flash by setting SW3[4] to ON, RCW[0:8] is set to 0_0111_xxxx using SW1[1:8] and SW2[1]), different U-Boot image can be selected to boot up the board, by setting SW3[5:7]. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide...
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Page 30: Chapter 3 Cpld Specification
Boot configuration override register (BOOTOR) Boot configuration register 1 (BOOTCFG1) Boot configuration register 2 (BOOTCFG2) 3.1.2 Chip ID1 register (CHIPID1) Offset Register Offset CHIPID1 QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 30 / 44... -
Page 31: Chip Id2 Register (Chipid2)
Fields Field Function CHIPID2 CHIPID2 0xaa, Identification of the CPLD image. 3.1.4 Hardware version register (HWVER) Offset Register Offset HWVER Function Hardware version register. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 31 / 44... -
Page 32: Software Version Register (Swver)
3.1.5 Software version register (SWVER) Offset Register Offset SWVER Diagram Bits SW_VER Reset Fields Field Function SW_VER SW_VER The version field of the CPLD software. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 32 / 44... -
Page 33: Reset Control Register (Rstcon)
1: Writing logic 1 generates 10GEDC PHY(CS4315) reset# signal; this bit can auto clear. XGT_RST XGT_RST 0: No reset occurs. Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 33 / 44... -
Page 34: Flash Control And Status Register (Flhcsr)
0: NOR flash bank select bit1 of switch status is 0. 1: NOR flash bank select bit1 of switch status is 1. Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 34 / 44... -
Page 35: Thermal Control And Status Register (Thmcsr)
Reset Fields Field Function THM_FAULT THM_FAULT 0: Thermal sensor no fault occurs. 1: Thermal sensor fault output. THM_ALERT Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 35 / 44... -
Page 36: Panel Led Control And Status Register (Ledcsr)
Diagram Bits STS_LED Reserved Reset Fields Field Function STS_LED STS_LED 0: Panel STATUS LED on. 1: Panel STATUS LED flash at 0.5 s. — QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 36 / 44... -
Page 37: Sfp+ Control And Status Register (Sfpcsr)
0: SFP+2 module not inserted 1: SFP+2 module inserted SFP2_TXDIS SFP2_TXDIS 0: SFP+2 TX enable 1: SFP+2 TX disable SFP2_RXLOS Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 37 / 44... -
Page 38: Miscellanies Control And Status Register (Misccsr)
11: Enable POR for software reset command POR_EN Reserved — PEX_PRS PEX_PRS 0: PCIe x4 card not present Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 38 / 44... -
Page 39: Boot Configuration Override Register (Bootor)
0: Boot configuration from CPLD overrides disable 1: Boot configuration from CPLD overrides enable 3.1.13 Boot configuration register 1 (BOOTCFG1) Offset Register Offset BOOTCFG1 QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 39 / 44... -
Page 40: Boot Configuration Register 2 (Bootcfg2)
Fields Field Function cfg_rcw_src8 cfg_rcw_src8 RCW source bit 8. — cfg_svr cfg_svr cfg_svr bits for Power-on Reset using. Table continues on the next page... QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 40 / 44... - Page 41 NXP Semiconductors CPLD Specification Table continued from the previous page... Field Function — cfg_eng_use cfg_eng_use cfg_eng_use bits for Power-on Reset using. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 41 / 44...
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Page 42: Appendix A Revision History
Updated Figure 3 to add x2 FDMF5820DC devices. Reset Replaced AQR1202 PHY with x2 AQR113C PHYs in Figure Rev. 0 06/2015 Initial public release. QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021 User Guide 42 / 44... - Page 43 Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice.
- Page 44 © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 08/2021 Document identifier: T2080RDBPCUG...