Clock Speed 1 (Clk_Spd1) - NXP Semiconductors QorIQ LS1028A Reference Manual

Clock Speed 1 (CLK_SPD1)

4.28 Clock Speed 1 (CLK_SPD1)
4.28.1 Address
Register
CLK_SPD1 030h
4.28.2 Function
The CLK_SPD1 register is used to report the user-selectable speed settings (typically
from switches) for the SYSCLK and DDRCLK clocks.
Values in the CLK_SPD1 register are used by boot software accurately initialize timing-
dependent parameters, such as for UART baud rates, I2C clock rates, and DDR memory
timing.
4.28.3 Diagram
Bits 7
R
W
NONE
4.28.4 Fields
Field
7-4 Reserved.
-
3-0 SYSCLK Rate Selection:
SYSCLK
0010= 100.00 MHz (fixed)
Other values are Reserved.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
86
6 5 4
0000
Confidential Proprietary
Offset
3 2
SYSCLK
Function
1 0
0010
NXP Semiconductors