Reset Status (Rst_Stat) - NXP Semiconductors QorIQ LS1028A Reference Manual

Field
1= Reset will not be asserted to the DDR DIMMs/devices. With proper DDR controller setup and careful
software setup DDR contents can survive resets.
This bit is not cleared with a general reset, but is preserved, as long as power is available. It is expected
that software that sets this bit is also responsible for clearing it.
2-1 Reserved.
-
0 Reset:
RST 0= Reset sequencer operates normally.
1= Upon transition from 0 to 1, restart the reset sequence.

4.32 Reset Status (RST_STAT)

4.32.1 Address
Register
RST_STAT 041h
4.32.2 Function
The RST_STAT register reports the current status of various reset-related signals.
4.32.3 Diagram
Bits 7
R WAIT
W
NONE 0
4.32.4 Fields
Field
7 Reset Waiting:
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
6 5
SYSRST
0
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Confidential Proprietary
Chapter 4 Qixis Programming Model
Function
Offset
4 3
HRST
000
Function
2 1 0
PORST RREQ
0 0 0
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