NXP Semiconductors QorIQ LS1028A Reference Manual page 31

RGMII
(OVDD)
ECx_GTX_CLK125
ECx_TXD0
ECx_TXD1
ECx_TXD2
ECx_TXD3
ECx_TX_CTL
ECx_GTX_CLK
ECx_RXD3
ECx_RXD2
ECx_RXD1
ECx_RXD0
ECx_RX_CTL
ECx_RX_CLK
SERDES RX
(LANE-A) TX
EMI1_MDC
EMI1_MDIO
LS1028
GPIO1_25
Table 2-5. Hardware bootstrap settings for SGMII PHY
Setting
PHY_AD[2:0]
MODE[3:0]=0001
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
IEEE-1588 INTERFACE
I1588_PULSE_OUT[1]
I1588_PULSE_OUT[2]
I1588_TRIG_IN[1:2]
I1588_ALARM_OUT[1:2]
I1588_CLK_OUT
IEEE_TSTCLK
PI3L50
0-A
TSEC_1588_CLK_IN
2V5 2V5
1.5K 1.5K
TRANSLATOR
MDC
MAX14591
MDIO
1.8V  2.5V
3V3
4.7K
SYSTEM
PHY_RST
RSTB
CPLD
3V3
4.7K
INTB
XTAL
25MHz
R160
R162
R163
R416
R415
PHY #1
R160, R159 & R163 : P HY ADDRES S = 002
R414
R413, R414, R415 & R416 : MO DE 0001
Figure 2-9. SGMII and IEEE 1588
PHY address = 0b00010
SGMII<=>UTP
Confidential Proprietary
Chapter 2 LS1028ARDB Functional Description
TSM-106-01-S-DV-A-P
(3,1)
2
1
(2,4)
3 4
RST_IEEE_B
(5,7)
5 6
from CPLD
(8)
7 8
(9)
9 10
11 12
1588 Access
Header
QUALCOMM AR8033
48-PIN QFN
1GB
MDI_0_P/N
#1
MDI_1_P/N
RJ-45 with
MDI_2_P/N
Transformer
MDI_3_P/N
100MB
PHY #1
SUPPORT
MODES: SGMII
4.7uH
1V0
LX
DVDDL
0 ohm
AVDDL
3V3
AVDD33
VDD33
VDDIO_REG 2V5
2V5
VDDH_REG
E1_RXD0/PHYADDR0
E1_RXD1/PHYADDR1
E1_ACT/PHYADDR2
E1_RX_CTL/MODE0
E1_RXD2/MODE1
E1_RXCLK/MODE2
E1_RXD3/MODE3
3V3
10K E1_RXD0/PHYADDR0 R158 10K DNP
E1_RXD1/PHYADDR1
10K DNP R159
10K
E1_ACT/PHYADDR2
10K R164 10K DNP
E1_RX_CTL/MODE0
R413 10K
E1_RXD2/MODE1
10K
E1_RXCLK/MODE2
10K
E1_RXD3/MODE3
10K
Description
1588 1PPS
31