NXP Semiconductors QorIQ LS1028A Reference Manual page 104

Board Configuration 5 (BRDCFG5)
4.46.1 Address
Register
BRDCFG5 055h
4.46.2 Function
The BRDCFG5 register manages uBUS1 connections and status.
4.46.3 Diagram
7
Bits
R U1A
W
RRST
X
4.46.4 Fields
Field
7 U1A reports the current 3.3V LVTTL level on the AN analog output pin.
U1A
6 U1I reports the current 3.3V LVTTL level on the IRQ interrupt pin.
U1I
5 U1R reports the current 3.3V LVTTL level on the RST pin.
U1R
4 Reserved.
-
3-2 Manages the uBUS1 IRQ input pin:
U1IRQ 00= IRQ pin treated as active-low interrupt input.
01= IRQ pin treated as active-high interrupt input.
10= IRQ pin treated as output, asserted low.
11= IRQ pin treated as output, asserted high.
1-0 Manages the uBUS1 RST output pin:
U1RST 00= RST pin tri-stated.
01= reserved.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
104
6 5
U1I U1R
X X
Confidential Proprietary
Offset
4 3 2
U1IRQ
0 00
Function
1 0
U1RST
00
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