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NXP Semiconductors QorIQ LX2160A Manual

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QorIQ LX2160A Reference Design
Board Reference Manual
Supports LX2160ARDB Revision B
Document Number: LX2160ARDBRM
Rev. 0, 09/2018

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Summary of Contents for NXP Semiconductors QorIQ LX2160A

  • Page 1 QorIQ LX2160A Reference Design Board Reference Manual Supports LX2160ARDB Revision B Document Number: LX2160ARDBRM Rev. 0, 09/2018...
  • Page 2 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 3: Table Of Contents

    2.12 CAN interface................................. 47 2.13 JTAG port..................................48 2.14 Interrupt controller................................48 2.15 GPIO access..................................50 2.16 Temperature measurement..............................51 2.17 LEDs....................................52 2.18 DIP switches................................... 55 2.19 System controller ................................58 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 4 3.22 LOS Status (LOS)................................86 3.23 Watchdog (WATCH)..............................87 3.24 Power Control/Status Registers............................89 3.25 Power Control 2 (PWR_CTL2)............................89 3.26 Power Event Trace (PWR_EVENT)..........................90 3.27 Power Status 0 (PWR_MSTAT).............................91 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 5 3.52 DUT Configuration 2 (DUTCFG2)..........................116 3.53 DUT Configuration 6 (DUTCFG6)..........................117 3.54 DUT Configuration 11 (DUTCFG11)..........................118 3.55 DUT Configuration 12 (DUTCFG12)..........................119 3.56 IRQ Management Registers............................120 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 6 3.65 Core Management Space Registers..........................129 3.66 Core Management Address (CMSA)..........................130 3.67 Core Management Data (CMSD)........................... 131 3.68 Switch Manager Registers.............................. 131 3.69 Switch Control (SWS_CTL)............................132 3.70 Switch Sample Status (SWS_STAT)..........................133 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 7: Lx2160Ardb Overview

    The QorIQ LX2160A reference design board (RDB) provides a comprehensive platform that enables design and evaluation of the QorIQ LX2160A processor. The LX2160ARDB comes pre-loaded with a board support package (BSP) based on a standard Linux kernel. The board comes in a 1U rackmount chassis form factor. It is lead-free and RoHS-compliant.
  • Page 8 Quad serial peripheral interface Reset configuration word RDIMM Registered dual inline memory module Real time clock Request to send SATA Serial advanced technology attachment Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 9: Related Documentation

    QorIQ LX2160A Product Provides a brief overview of the LX2160A processor QorIQ LX2160A Product Brief Brief QorIQ LX2160A Data Sheet Provides information about electrical characteristics, hardware Contact FAE / sales design considerations, and ordering information representative QorIQ LX2160A Family Provides a detailed description about the LX2160A QorIQ...

  • Page 10: Block Diagrams

    Table 1-2. Related documentation (continued) Document Description Location / how to access QorIQ LX2160A Chip Errata Lists the details of all known silicon errata for the LX2160A Contact FAE / sales representative QorIQ LX2160A Design This document provides recommendations for new designs...
  • Page 11 4 x GPIO Core Complex Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements Figure 1-1. LX2160A block diagram The figure below shows the LX2160ARDB block diagram. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 12: Board Features

    Up to 32 GB at 3200 MT/s SystemID Power supplies uATX USB_HVDD GVDD SD_SVDD OVDD 3.3V 5VSB Figure 1-2. LX2160ARDB block diagram 1.4 Board features The table below lists the features of the LX2160ARDB. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 13 16 Arm Cortex -A72 processor cores based on 32-/64-bit Armv8 architecture, supporting speeds of up to 2.2 GHz NOTE: For more details on the LX2160A processor, see QorIQ LX2160A Family Reference Manual. DDR memory Two 72-bit DDR4 Each DDR4 port supports: ports (64-bit data, 8-bit •...

  • Page 14: Board Top View

    • Implements registers for system control and monitoring • General fault monitoring and logging 1.5 Board top view The figure below shows the top-side view of the LX2160ARDB. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 15 Chapter 1 LX2160ARDB Overview Figure 1-3. LX2160ARDB top view QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 16 Board top view QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 17: Lx2160Ardb Functional Description

    I2C interface • UART interface • CAN interface • JTAG port • Interrupt controller • GPIO access • Temperature measurement • LEDs • DIP switches • System controller QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 18 LX2160A SD_OVDD 1.80V @ 5A PS_SD_OVDD_SEL MC34717EP/R2 SD_SVDD SD_VDD_FLT PS_SD_VDD_EN LX2160A SD_SVDD PS_SD_VDD_PG 0.92V @ 5A from CPLD SD3_VDD_FLT LX2160A SD3_SVDD Figure 2-1. Power supplies - Part 1 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 19 3.30V @ 1.0A PS_EVDD_EN from CPLD 12V0 IN112525 0V85 AQR107_1 VDD 0.85V @ 20A LTC7150 AQR107_2 VDD PS_0V85_EN DIMM[1:4] VDD PS_0V85_PG from CPLD Figure 2-2. Power supplies - Part 2 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 20 Table 2-1. Primary power supply Power supply Description External ATX 12 V power 90 - 264 Vac supply Fin frequency 50 - 60 Hz Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 21 Technology accuracy LX2160A general I/O drivers. OVDD also supplies power to the PROG_MTR and TA_PROG_SFP pins, through J8 and J9 jumpers, respectively, Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 22 1.8 V and 3.3 V on command of the SDHC IP block for certain board configurations. NOTE: FPF1321UCX is a power switch, not a power supply. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 23 • The SW_AUTO_ON switch (SW4[2]) is set to '1' On receipt of a power event signal, the CPLD power sequencer block manages the orderly enable of the remaining power supplies, as shown in the figure below. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 24 OVDD, EVDD, 530-540mS AVDD_** ~540mS ~540mS USB_SVDDn, USB_SDVDDn 550-570mS 550-570mS SD_SVDD 580-610mS SD_OVDD, AVDD_SDn_PLLn ~610mS GVDD ~610mS DDRn_VTT, DDRn_VREFCA >= 700mS DUT_PORESET_B Figure 2-5. Power up voltage sequence QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 25: Clocks

    2.2 Clocks The LX2160ARDB provides all the clocks required for the processor and peripheral interfaces. The figure below shows the LX2160ARDB clock architecture. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 26 All the clocks are fixed frequency, and most are produced by the Si5341B or Si52208. The following table summarizes the specifications of each clock and the component that provides it. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 27 1.8 V OUT8: CLK_SD1_F_[P, N] • Frequency: SerDes1 controller 161.1328125 MHz PLL 1 • Output type: HCSL • Operating voltage: 1.8 V Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 28: Ddr Interface

    CLK_SD3_S_[P, N] PLL 2 2.3 DDR interface The LX2160ARDB supports two high-speed DDR4 memory ports: DDR#1 and DDR#2. The figure below shows the architecture of the DDR#1 memory port. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 29 (2.5 V I/O shifted) 0x51 0x52 I2C1_CH0_2V5 DDR4 UDIMM 288-pin sockets Figure 2-7. DDR#1 memory port architecture The figure below shows the architecture of the DDR#2 memory port. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 30 • DIMM#1 (J14/J15) supports four chip selects (D1_MCS_B[0:3] / D2_MCS_B[0:3]) for single-, dual-, and quad-rank DDR4 memory modules • DIMM#2 (J16/J17) supports two chip selects (D1_MCS_B[2:3] / D2_MCS_B[2:3]) for single- and dual-rank DDR4 memory modules QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 31: Serdes Interface

    The LX2160A processor supports three SerDes modules (SerDes1, SerDes2, and SerDes3), each having eight high-speed serial communication lanes. Each SerDes lane supports speeds of up to 25 GHz. The figure below shows the LX2160ARDB SerDes architecture. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 32 Protocol #2 Gen 1-4 Figure 2-9. SerDes architecture The figure below shows the possible SerDes protocol combinations that can be used on the LX2160ARDB with the LX2160A processor. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 33 1. A right-angle adapter is required to connect a PCIe Gen 1/2/3 connector. No adapter is required when using a PCIe Gen 4 connector. NOTE No muxes or other configuration is required for SerDes operation. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 34: Ethernet Controller Interface

    EC2_RX_DV EC2_RXD[3:0] EC2_RX_CLK EC2_GTX_CLK IEEE 1588 Header EC_GTX_CLK125 EC_CLK125 from CLKGEN CFG_MUX_EC2 from CPLD RST_PHY1_B from CPLD RST_PHY2_B from CPLD RST_GEN_OVDD_B from CPLD Figure 2-11. Ethernet controller architecture QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 35: Ethernet Management Interface

    All remaining IEEE 1588 signals are connected to the dedicated header pins 2.6 Ethernet management interface The LX2160ARDB has two Ethernet management interfaces, EMI1 and EMI2, for controlling PHY transceivers. The figure below shows the PHY device connections. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 36: Esdhc Interface

    0x02 Qualcomm AR8035 1 GbE PHY #2 0x04 Aquantia AQR107 10 GbE PHY #1 0x05 Aquantia AQR107 10 GbE PHY #2 EMI2 0x00 Inphi IN112525 25 GbE PHY QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 37 FBGA169 device or an FBGA153 device. By default, an FBGA169 eMMC device is supported. The table below shows the devices supported by the eSDHC2 interface. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 38: Xspi Interface

    XSPI chip-select signals from the processor are driven to the XSPI memories or the QSPI emulator through two high-speed multiplexers. The XSPI interface supports Single/Dual/ Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines). The figure below shows the LX2160ARDB XSPI connections. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 39 SW1[6:8] BRDCFG0[7:5] Bit value XSPI_A_CS XSPI_A_CS1 Descriptio 000 (default Dev #0 Dev #1 Boot from setting) default flash memory Dev #1 Dev #0 Boot from alternative flash memory QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 40: Usb Interface

    As described in the table above, operating modes for USB1 and USB2 ports are controlled through the J31 and J33 jumpers, respectively. The figure below shows the architecture of the LX2160ARDB USB interface. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 41 USB connected device is 2 A per channel. Each USB connector has an LED nearby, USB1_5V and USB2_5V, which are active when the +5 V USB power supply is enabled. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 42: I2C Interface

    All boot-software-dependent devices are placed on channel 0, or "I2C1_CH0" as it is named. Channel 0 is the default selection upon reset so that software has immediate access to critical resources. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 43 Table 2-14. I2C bus device map I2C bus 7-bit address Device Description Notes (All) I2C master LX2160ARDB 0x66 I2C slave CPLD I2C access to CPLD BCSRs (registers). Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 44 NXP PCA9547PW I2C bus multiplexer Converts I2C1_CH7 (secondary) channel into eight sub- channels I2C1_CH7_CH0 0x50 Quad SFP+ cage 40G MAC2 QSFP+ port Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 45: Uart Interface

    LX2160ARDB, the UART ports are available for external connection through a dual-port stacked DB9 male connector. Two RS-232 transceivers (Linear Technology LTC2804-1) translate the signals to RS-232 levels. The figure below shows the UART architecture. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 46 UART3_SIN/UART4_SIN and the UART1_CTS_B/UART2_CTS_B signal becomes UART3_SOUT/UART4_SOUT. To evaluate UART3 and/or UART4, a custom DB9 interface cable must be created, as shown in the following figure. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 47: Can Interface

    Dual-stack DB9 male CAN2 SN74LVC2T45 From CAN1 (top) XCVR TJA1051T/3 CAN1 SN74LVC2T45 From CAN2 (bottom) XCVR TJA1051T/3 NORC OMP CFG_CAN_EN_B 178-009-613R571 From CPLD or equivalent Figure 2-22. CAN architecture QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 48: Jtag Port

    RTC and different Ethernet PHYs. The remaining pins are used to merge various board- related interrupt sources for handling by the processor, or for general GPIO use. The interrupts are connected as shown in the figure below. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 49 IRQ9_B PHY_25G_LOL (if SFP2_MOD_ABS is low) SFP2 transceiver loss-of-lock interrupt IRQ10_B PHY_25G_LOL (if SFP3_MOD_ABS is low) SFP3 transceiver loss-of-lock interrupt IRQ11_B IRQ_QSFP_B zQSFP+ transceiver (40 GbE PHY) interrupt QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 50: Gpio Access

    By programming the RCW “IRQ_EXT” field properly, an unused IRQ pin can be reassigned to GPIO purposes. Event signals from EVT pins EVT[0:4] flow through a 5- pin GPIO header. The table below shows the GPIO mapping in the LX2160ARDB. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 51: Temperature Measurement

    LEDs. The CPLD uses these signals to power down the system, to protect the processor from over-temperature damage. The LX2160ARDB thermal management scheme is shown in the figure below. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 52: Leds

    This may be necessary if operating the board    without a processor installed, as an open thermal diode   connection will measure as 127 °C. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 53 Green General status. See Multi-status LEDs for details. Green Green Green Green Green Green Green Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 54 Reset Sequencer state Live I2C1_SCL activity Live I2C remote activity (see Table 2-21) Same as M[3:2], except that short pulses are stretched to 500 ms for easier detection QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 55 Start reset due to pushbutton switch RECONFIG 1110 = 0xE Start reset due to reconfig request via RCFG[GO] = 1 POST_RST 1111 = 0xF Wait for reset requests to clear QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 56: Dip Switches

    QSPI emulator DEV#1 Boot from QSPI emulator, program alternative flash memory DEV#0 QSPI emulator Emulator access SW2[1] PCIe Spread-Spectrum SW_SPREAD enable Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 57 NOTE: Do not change the default setting of this switch. SW3[8] Unused Reserved with 0 as the default setting SW4[1] Bypass mode SW_BYPASS_B Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 58: System Controller

    The LX2160ARDB system controller (or “CPLD” for short) controls the operation of the system, including: • AC power supply control • Onboard regulator control and sequencing • Reset assertion to processor and devices • Processor and system configuration QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 59 HOT_CLK 25 MHz 25 MHz PCB_REV[2:0] 000 = “Rev A” 3.3V LVCMOS 001 = “Rev B” Selectively DNP resistors to encode PCB rev Figure 2-27. System controller architecture QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 60 The system controller is powered continuously using the 3.3 V and 1.8 V regulators, powered from the ATX PSU +5 V standby power. This allows it to control all aspects of board bring-up, including initial power sequencing. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 61 TEST_SEL_B TEST_SEL_B SW3[1] DUTCFG2[0] Silicon variations CFG_ENG_USE0 XSPI1_A_SCK SW2[6] DUTCFG11[7] Specifies whether single ended or differential clock is used in the SoC Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 62 Triggered by the SW_PWR_B signal, or by setting switch SW_AUTO_ON=1. Enable ATX power supply. Enable ATX PSU, wait for it to report “power good”. LX2160A PORESET_B is asserted during power-up. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 63 • JTAG_RST_B • SW_RST_B Sample switches. Internal registers are reset to default values. Registers that default to switch values are set now. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 64 Reset sequence complete. The CPLD has finished reset management. The reset sequencer watches for reset switch events and will restart at reset sequencer step 1 if any are detected. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 65: Qixis Programming Model

    10110000b 01Dh LOS Status (LOS) 00000000b 01Fh Watchdog (WATCH) xxxxxxxb 021h Power Control 2 (PWR_CTL2) 00000000b 022h Power Event Trace (PWR_EVENT) 00000000b Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 66 Interrupt Drive 5 (IRQDRV5) 00000000b 0D8h Core Management Address (CMSA) 00000000b 0D9h Core Management Data (CMSD) 00000000b 0DCh Switch Control (SWS_CTL) 00000101b 0DDh Switch Sample Status (SWS_STAT) 10000000b QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 67: Register Conventions

    General Reset: always reset, for any reason. Generally, a register is wholly affected by only one reset source, however there are exceptions and these are shown with separate reset lines for each reset source. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 68: Identification Registers

    The ID number remains same for all board revisions. 3.4.3 Diagram Bits NONE 3.4.4 Fields Field Function The board-specific identifier for the system. 42h= LX2160ARDB QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 69: Board Version (Ver)

    The ARCH field starts at 1 and is only changed if major software-impacting architectural changes to the board occur: changes to PHY vendors, memory devices, etc. PCB board version: 1= Rev A (or pre-release) 2= Rev B (etc.) QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 70: Qixis Version (Qver)

    Minor revision information may be found in the MINOR register. 3.6.3 Diagram Bits QVER NONE 00000001 3.6.4 Fields Field Function Qixis version as a decimal value: QVER 1= Version 1 2= Version 2 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 71: Programming Model (Model)

    Model Register Encoding: 0= Lower 4 bits contain programming model revision (MODEL). 1= reserved. Reserved. Model (BOM Version) Information: MODEL 0000= No revision: PCB version is 'A', 'B', etc. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 72: Minor Revision (Minor)

    V%d", qver ); if (minor != 0) { printf(".%d", minor ); Note: setting the MINOR/MINTAG register to 5h before reading is optional, as on every reset 05h is the default. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 73: Control And Status Registers

    3.8.4 Diagram Bits MINOR NONE 3.8.5 Fields Field Function Read: Data to read from MINOR/MINTAG. MINOR Write: Address of data to read. 3.9 Control and Status Registers QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 74: General Control (Ctl)

    1= ALARM register reads return the alarm mask. This bit directly drives the XTEST signal, typically driving an SMA connector. The function is user-defined. XTEST Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 75: Auxiliary (Aux)

    The AUX register may be used by software to store information. The AUX register is initialized to zero when the system is powered-up, and never altered by hardware again. 3.11.3 Diagram Bits ARST 00000000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 76: System Status (Stat_Sys)

    3.12.3 Diagram Bits BBOX ALARMED ALTERED ASLEEP NONE ~SW_BBOX 3.12.4 Fields Field Function Reserved. BootBox Mode Selected: BBOX 0= The system operates normally. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 77: Alarm (Alarm)

    Write 1 to an ALARM register bit to prevent Qixis from recognizing that alarm condition. By default, all alarms are handled. 3.13.3 Diagram Bits PSEQ VTOFF ORIENT TWARN TALERT ARST QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 78: Presence Detect 1 (Stat_Pres1)

    1= The temperature has exceeded fault limits. NOTE: This signal may be asserted by either SA56004 thermal monitor. The temperature limits depend upon software programming. 3.14 Presence Detect 1 (STAT_PRES1) QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 79 0= Processor type (EFFID) is based on device. 1= Processor type (EFFID) was overridden using SW_CPU_FORCE. Reserved. Normal Processor ID: CPUID Same values as EFFID, but unaltered by SW_CPU_FORCE. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 80: Presence Detect 2 (Stat_Pres2)

    SGMII slots. 3.15.3 Diagram Bits SLOT2 SLOT1 NONE 111111 3.15.4 Fields Field Function Reserved. (same as SLOT1) SLOT2 0= a card is installed. SLOT1 1= no card is installed. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 81: Led Control (Led)

    CTL[LED] is set to 1; otherwise they are used to display general system activity. 3.16.3 Diagram Bits GRST 00000000 3.16.4 Fields Field Function LED Status Control: 0= LED M[bitno] is off. 1= LED M[bitno] is on. 3.17 Reconfiguration Registers QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 82: Reconfiguration Control (Rcfg)

    Field Function Reserved. Immediate changes for BRDCFG registers: LIVE 1= BRDCFG registers outputs occur immediately. For QixMin, LIVE is always 1. Reserved. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 83: Sfp Csr 1 (Sfp1)

    3.19.1 Address Register Offset SFP1 018h 3.19.2 Function The SFP1 register controls and monitors the zQSFP+ cage used with the 40GE PHY (40G MAC2). 3.19.3 Diagram Bits LPMODE CRST QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 84: Sfp Csr 2 (Sfp2)

    3.20 SFP CSR 2 (SFP2) 3.20.1 Address Register Offset SFP2 019h 3.20.2 Function The SFP2 register controls and monitors the SFP+ cage used with the 25G PHY #1 (25G MAC5). QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 85: Sfp Csr 3 (Sfp3)

    1= SFP module reports receive loss-of-signal. Reserved. SFP2_TX_EN Control: TXEN_B 0= SFP module transmitter is enabled. 1= SFP module transmitter is disabled. 3.21 SFP CSR 3 (SFP3) 3.21.1 Address Register Offset SFP3 01Ah QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 86: Los Status (Los)

    0= SFP module reports no receive errors. 1= SFP module reports receive loss-of-signal. Reserved. SFP3_TX_EN Control: TXEN_B 0= SFP module transmitter is enabled. 1= SFP module transmitter is disabled. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 87 1= Retimer has lost lock on one or more lanes. Note: Since the 25G retimer services a pair of independent lanes, the global lock reporting is less useful. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 88: Watchdog (Watch)

    Watchdog timer value, as determined by the formula: WATCH time-out = [ WATCH * (2.0sec) ] + 2.0sec Examples: 11111111= 8 min 00111111= 2 min 00001111= 32 sec QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 89: Power Control/Status Registers

    3.25 Power Control 2 (PWR_CTL2) 3.25.1 Address Register Offset PWR_CTL2 021h 3.25.2 Function The PWR_CTL2 register is used to control system power-on/power-off events. 3.25.3 Diagram Bits CRST 0000000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 90: Power Event Trace (Pwr_Event)

    3.26 Power Event Trace (PWR_EVENT) 3.26.1 Address Register Offset PWR_EVENT 022h 3.26.2 Function The PWR_EVENT register records which events caused power-on or -off events. 3.26.3 Diagram Bits PPEVENT PEVENT NONE 0000 0000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 91: Power Status 0 (Pwr_Mstat)

    3.27.2 Function The PWR_MSTAT register monitors the overall power status of the board, including that of the main (ATX or other) power supply used to power all other rails. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 92: Power Status 1 (Pwr_Stat1)

    SSTATE 11= S3 - completely on Note: If a device does not support hardware (i.e external) power savings modes, S3 is always reported. 3.28 Power Status 1 (PWR_STAT1) QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 93 1= Power supplies are operating. LVAUX Power Supply Status: LVAUX 0= Power supply is disabled or faulted. 1= Power supply is operating. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 94: Power Status 2 (Pwr_Stat2)

    3.29 Power Status 2 (PWR_STAT2) 3.29.1 Address Register Offset PWR_STAT2 026h 3.29.2 Function Monitors various power statuses; see PWR_STAT1 for details. 3.29.3 Diagram Bits TA_BB OVDD VTT2 VTT1 GVDD NONE QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 95: Clock Control Registers

    1= Power supply is operating. 3.30 Clock Control Registers The clock control registers control programmable clock synthesizers used to supply clocks to the processor and associated peripherals. 3.31 Clock Speed 1 (CLK_SPD1) QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 96: Clock Id/Status (Clk_Id)

    3.31.4 Fields Field Function DDRCLK Rate Selection: DDRCLK 0000= 100.00 MHz (fixed) Other values are Reserved. SYSCLK Rate Selection: SYSCLK 0000= 100.00 MHz (fixed) Other values are Reserved. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 97: Reset Control Registers

    3.32.3 Diagram Bits NONE 0000 0000 3.32.4 Fields Field Function Reserved. System Clock ID = 0000 (NONE) CLK0= SYSCLK is fixed on this system. 3.33 Reset Control Registers QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 98: Reset Control (Rst_Ctl)

    3.34.4 Fields Field Function Reserved. 00= Disabled - do nothing. REQMD 01= reserved 10= reserved 11= Normal - assert PORESET_B to DUT to begin normal reset sequence. Reserved. Reset: QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 99: Reset Status (Rst_Stat)

    1= Reset sequencer is in RMT-WAIT state, waiting for permission to proceed. System Reset: SYSRST 0= System is operating normally. 1= System is in reset. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 100: Reset Event Trace (Rst_Reason)

    Register Offset RST_REASON 042h 3.36.2 Function The RST_REASON register is used to report the cause of the most-recent reset cycle. 3.36.3 Diagram Bits PREV REASON NONE 1111 0000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 101: Reset Force 1 (Rst_Force1)

    As long as a bit is set to 1, the reset signal to grouped devices will be asserted. Resetting a resource while in used by the bootloader or OS will typically cause crashes, etc. Use carefully. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 102: Reset Force 2 (Rst_Force2)

    Reset DIMMs on DDR port #3 MEM2 1= Assert RST_MEM2_B Reset DIMMs on DDR port #1 MEM1 1= Assert RST_MEM1_B 3.38 Reset Force 2 (RST_FORCE2) 3.38.1 Address Register Offset RST_FORCE2 044h QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 103: Reset Force 3 (Rst_Force3)

    PORST NOTE: This bit only asserts the signal to the DUT; it is not intended to be used as a general system reset. 3.39 Reset Force 3 (RST_FORCE3) QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 104: Reset Mask 1 (Rst_Mask1)

    Bits SLOT1 SLOT2 IEEE GRST 00000 3.39.4 Fields Field Function 1= Assert RST_SLOT1_B. SLOT1 1= Assert RST_SLOT2_B. SLOT2 Reserved. 1= Force RST_IEEESLT_B. IEEE 3.40 Reset Mask 1 (RST_MASK1) QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 105 3.40.4 Fields Field Function 1= Mask RST_CLKGEN_B. 1= Mask RST_XSPI_B. XSPI 1= Mask RST_QSFP_B. QSFP 1= Mask RST_I2CMUX_B. I2CMUX 1= Mask RST_EMMC _B Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 106: Reset Mask 2 (Rst_Mask2)

    EPHY2 EPHY1 PHY10 PHY25 PHY40 TRST HRST PORST ARST 3.41.4 Fields Field Function 1= Mask RST_EPHY2_B for the RealTek PHY #2. EPHY2 Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 107: Reset Mask 2 (Rst_Mask3)

    3.42 Reset Mask 2 (RST_MASK3) 3.42.1 Address Register Offset RST_MASK3 04Dh 3.42.2 Function Masks selected reset sources. See RST_FORCE1 for details. 3.42.3 Diagram Bits SLOT1 SLOT2 IEEE ARST 00000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 108: Board Configuration Registers

    128 control options; however, not every platform implements all the registers. 3.44 Board Configuration 0 (BRDCFG0) 3.44.1 Address Register Offset BRDCFG0 050h 3.44.2 Function The BRDCFG0 register is commonly used to select IFC and QSPI boot devices. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 109: Board Configuration 1 (Brdcfg1)

    011= DEV #1 100= DEV #0 Reserved. 3.45 Board Configuration 1 (BRDCFG1) 3.45.1 Address Register Offset BRDCFG1 051h 3.45.2 Function The BRDCFG1 register shows/controls SYSCLK and DDRCLK speeds. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 110: Board Configuration 2 (Brdcfg2)

    All other values are reserved. Reserved. SYSCLK Frequency Selection: SYSCLK 00= 100.00 MHz (fixed) All other values are reserved. 3.46 Board Configuration 2 (BRDCFG2) 3.46.1 Address Register Offset BRDCFG2 052h QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 111: Board Configuration 3 (Brdcfg3)

    SerDes2 Clock #1 (F) Rate: SD2CK1 00= 100.0000000 MHz (fixed) SerDes2 Clock #2 (S) Rate: SD2CK2 00= 100.0000000 MHz (fixed) 3.47 Board Configuration 3 (BRDCFG3) 3.47.1 Address Register Offset BRDCFG3 053h QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 112: Board Configuration 4 (Brdcfg4)

    SerDes3 Clock #2 (S) Rate: SD3CK2 00= 100.0000000 MHz (fixed) Reserved. 3.48 Board Configuration 4 (BRDCFG4) 3.48.1 Address Register Offset BRDCFG4 054h 3.48.2 Function The BRDCFG4 register controls general board configuration. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 113 1= Slot clocks enabled always. PCI Express Spread-Spectrum Spread Level: SPRLVL 0= -0.25% spread. 1= -0.50% spread. Valid for Rev B or later boards only. PCI Express Spread-Spectrum Enable (net CFG_SPREAD): QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 114: Dut Configuration Registers

    3.50.1 Address Register Offset DUTCFG0 060h 3.50.2 Function The DUTCFG0 register is used to select the boot device used upon reset (cfg_rcw_src). 3.50.3 Diagram Bits RCWSRC RRST 0000 SW_RCW_SRC QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 115: Dut Configuration 1 (Dutcfg1)

    The DUTCFG1 register holds the LSB of cfg_rcw_src values when they are larger than 8 bits. For the LX2160ARDB, this register is ignored. 3.51.3 Diagram Bits RRST 11111111 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 116: Dut Configuration 2 (Dutcfg2)

    The DUTCFG2 register manages processor device selection (SVR) and internal-only device test features. 3.52.3 Diagram Bits SVR10 TEST RRST 11111 SW_SVR 3.52.4 Fields Field Function Reserved. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 117: Dut Configuration 6 (Dutcfg6)

    The DUTCFG6 register is used to sample device-specific test modes. 3.53.3 Diagram Bits SOCUSE SW_SOCUS RRST 111111 3.53.4 Fields Field Function Reserved. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 118: Dut Configuration 11 (Dutcfg11)

    ENGUSE2 RRST SW_ENGUS SW_ENGUS SW_ENGUS 11111 3.54.4 Fields Field Function ENG_USE0: Differential Clock Mode (cfg_enguse0): ENGUSE0 0= Processor uses differential SYSCLK_P/SYSCLK_N input. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 119: Dut Configuration 12 (Dutcfg12)

    The DUTCFG12 register is used to provide the general-purpose GPCFG signals. These settings are sampled by the processor for customers to use as desired, but have no hardware effects. 3.55.3 Diagram Bits RRST SW_GPIN 111111 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 120: Irq Management Registers

    Fan interrupt (from EMC2305) IRQ9 IN112525 PHY LOL if SFP2 MOD_ABS low IRQ10 IN112525 PHY LOL if SFP3 MOD_ABS low IRQ11 zQSFP+ transceiver (40G PHY) interrupt TMPDETB TMP_DETECT_B QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 121 IRQ6 IRQ7 NONE 1111 3.57.4 Fields Field Function Reserved. 1= IRQ1_B signal is high. IRQ1 Reserved. 1= IRQ6_B signal is high. IRQ6 1= IRQ7_B signal is high. IRQ7 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 122: Interrupt Status 1 (Irqstat1)

    Field Function Reserved. 1= IRQ9_B signal is high. IRQ9 1= IRQ10_B signal is high. IRQ10 1= IRQ11_B signal is high. IRQ11 Reserved. Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 123: Interrupt Control 0 (Irqctl0)

    The IRQCTL0 register allows defining interrupt output modes for IRQ[0:3], where relevant to the target system. 3.59.3 Diagram Bits IRQ1 CRST 3.59.4 Fields Field Function Reserved. Sets mode of IRQ1 output: Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 124: Interrupt Control 2 (Irqctl2)

    Register Offset IRQCTL2 096h 3.60.2 Function The IRQCTL2 register allows defining interrupt output modes for IRQ[8:11], where relevant to the target system. 3.60.3 Diagram Bits IRQ9 IRQ10 CRST QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 125: Interrupt Drive 0 (Irqdrv0)

    3.61 Interrupt Drive 0 (IRQDRV0) 3.61.1 Address Register Offset IRQDRV0 098h 3.61.2 Function The IRQDRV0 register allows control of selected interrupt pins. 3.61.3 Diagram Bits IRQ1 CRST 0000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 126: Interrupt Drive 1 (Irqdrv1)

    3.62 Interrupt Drive 1 (IRQDRV1) 3.62.1 Address Register Offset IRQDRV1 099h 3.62.2 Function The IRQDRV1 register allows control of selected interrupt pins. 3.62.3 Diagram Bits IRQ6 IRQ7 CRST 0000 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 127: Interrupt Drive 2 (Irqdrv2)

    3.63 Interrupt Drive 2 (IRQDRV2) 3.63.1 Address Register Offset IRQDRV2 09Ah 3.63.2 Function The IRQDRV2 register allows control of selected interrupt pins. 3.63.3 Diagram Bits IRQ9 IRQ10 IRQ11 CRST QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 128: Interrupt Drive 5 (Irqdrv5)

    The status of IRQ11_B can be monitored with the IRQSTAT registers. 3.64 Interrupt Drive 5 (IRQDRV5) 3.64.1 Address Register Offset IRQDRV5 09Dh 3.64.2 Function The IRQDRV5 register allows control of selected interrupt pins. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 129: Core Management Space Registers

    For RDB systems, only the following are defined: 3.65.1 CMS Registers Address Name Definition Number of configuration switches. 01..0F Image of configuration switch #n. Ranges not listed are reserved. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 130: Core Management Address (Cmsa)

    The CMSA register selects one of the internal core management registers within Qixis for subsequent read- or write-access via the CMSD register. 3.66.3 Diagram Bits ADDR ARST 00000000 3.66.4 Fields Field Function Select internal CMS register for read/write via CMSD. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 131: Core Management Data (Cmsd)

    CMSD contains the value of a CMS register selected by CMSA. See CMSA for details. 3.67.3 Diagram Bits DATA ARST 00000000 3.67.4 Fields Field Function Read/write internal CMS registers selected with CMSA. DATA 3.68 Switch Manager Registers QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 132: Switch Control (Sws_Ctl)

    3.69.2 Function The SWS_CTL register manages the switch sampler. 3.69.3 Diagram Bits POLL ARST 0000 3.69.4 Fields Field Function Reserved. Reserved. Poll Switches: Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...

  • Page 133: Switch Sample Status (Sws_Stat)

    SWS_STAT reports on update activity from the serial switch sampler. 3.70.3 Diagram Bits NONE 000000 3.70.4 Fields Field Function Updated: 0= (reserved) Table continues on the next page... QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 134 Switch Sample Status (SWS_STAT) Field Function 1= The switches were updated. Reserved. Reserved. QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 135 Appendix A Revision History The table below summarizes the revisions to this document. Table A-1. Revision history Revision Date Topic cross-reference Change description Rev. 0 09/2018 Initial public release QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 136 QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018 NXP Semiconductors...
  • Page 137 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or Home Page: fabricate any integrated circuits based on the information in this document. NXP reserves the right to nxp.com make changes without further notice to any products herein.

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