NXP Semiconductors QorIQ LS1028A Reference Manual page 25

The address and control/command signals to the DDR4 SDRAM memory chips are
routed in as per the Fly-by topology and are terminated to VTT (0.6 V). The data bus and
associated signals, such as DM and DQS/DQS_B have one-to-one byte wise connections
to the individual x8 DDR4 memories. The ECC nibble goes to the fifth DDR4 memory.
The part number of the SDRAM memory chips is MT40A1G8SA-075:E (from Micron
Technology).
Following are the characteristics of the LS1028A DDR4 memory controller:
• Up to 1.6 GT/s
• Supports 32-bit operation (with ECC support)
• Supports x8 devices
• Supports two chip selects, D1_MCS0_B and D1_MCS1_B; however, on board only
D1_MCS0_B chip select is supported
• IOs powered by 1.2 V power supply from MC34716EP switch regulator
The MC34716EP switch regulator generates the following different power supplies for
the DDR4 controller IO, memory devices, and terminations: VCC_GVDD_S (1.2 V),
VTT (0.6 V) and VREFCA (0.6 V). The memory interface including all the necessary
termination and I/O power are routed, as shown in the following figure.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
Chapter 2 LS1028ARDB Functional Description
Confidential Proprietary
25