I2C Interface - NXP Semiconductors QorIQ LS1028A Reference Manual

I2C interface

LS1028A
OVDD
(1.8V)
2.12 I2C interface
The LS1028A processor supports up to six I2C buses. The I2C1 port is used for system
setup and monitoring and the other ports should be programmed to be used for SDHC1
CD and WP , CAN 1 and 2 interfaces, GPIO, and USB2 PWRFAULT & DRVVBUS.
These secondary functionalities should be enabled in the RCW field.
The I2C1 port is connected to a PCA9848PWJ I2C multiplexer to isolate address
conflicts and to effectively manage the large number of I2C devices. The I2C1 port is
connected to the level shifter device NTSX2102GU8H (from NXP) to enable
bidirectional voltage level translation (1.8 V to 3.3 V and 3.3 V to 1.8 V) for CPLD and
external I2C devices.
The figure below shows the I2C bus architecture.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
36
OVDD (1.8V)
IIC3_SCL
LVC
IIC4_SCL
2T45
IIC3_SDA
LVC
IIC4_SDA
2T45
OE
CFG_DRV_INTERPOSER
from CPLD
Figure 2-12. CAN architecture
Confidential Proprietary
Dual-stack DB9 male
3V3
5V
CAN
XCVR
TJA1051T/3
3V3
5V
CAN
XCVR
TJA1051T/3
NORC OMP
178-009-613R571
CAN2
(top)
CAN1
(bottom)
or equiv
NXP Semiconductors